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參數(shù)資料
| 型號(hào)： | HDJD-J822-SCR00 |
| 英文描述： | Agilent HDJD-J822-SCR00 Color Management System Feedback Controller |
| 中文描述： | 安捷倫HDJD - J822 - SCR00色彩管理系統(tǒng)反饋控制器 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 118K |
| 代理商： | HDJD-J822-SCR00 |
10
I
2
C Timing (SDA, SCL)
Symbol
Parameter
Min.
Max.
Units
f
scl
t
HD:STA
t
HD:DAT
t
LOW
t
HIGH
t
SU:STA
t
SU:DAT
t
SU:STO
t
BUF
SCL clock frequency
0
100
kHz
(Repeated) START condition hold time
4.0
-
μ
s
μ
s
μ
s
μ
s
μ
s
ns
Data hold time
0
3.45
SCL clock low period
4.7
-
SCL clock high period
4.0
-
Repeated START condition setup time
4.7
-
Data setup time
250
-
STOP condition setup time
4.0
-
μ
s
μ
s
Bus free time between START and STOP conditions
4.7
-
Figure 1. I
2
C bus timing waveforms.
Notes:
1. The “Absolute Maximum Ratings” are those values beyond which damage to the device may occur. The device should not be operated at these
limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for actual device operation.
2. Unless otherwise specified, all voltages are referenced to ground.
3. A 1% precision resistor is recommended. This resistor is tied from the ROSC pin to ground.
4. V
REF
= V
REF_INT
in internal reference configuration. V
REF
= V
REF_EXT
in external reference configuration.
5. The voltage level at any of the SENSE_* pins must be lower than V
DDD
or V
DDA
(whichever is lower) by at least V
DIFF_SENSE
volts.
6. T
A
= 25
°
C. Room temperature.
7. Applies to all DI pins.
8. Guaranteed by design.
9. Applies to all DO pins. SDA is an open-drain NMOS. Minimum V
OH
depends on the pull-up resistor value.
10. Applies to all DO and DIO pins.
11. Dynamic testing is performed when the IC is operating in a mode representative of typical operation.
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:STA
t
SU:STO
t
BUF
S
SCL
SDA
Sr
P
S
t
HD:STA
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