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參數(shù)資料
| 型號(hào)： | HDD32M72B18RW-13B |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| 中文描述： | 256MB的DDR SDRAM內(nèi)存模塊（32Mx72bit），在16Mx8，4Banks，4K的參考依據(jù)。，184Pin與鎖相環(huán)內(nèi)存 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 169K |
| 代理商： | HDD32M72B18RW-13B |
HANBit
HDD32M72B18RPW
URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)
CK to valid DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
0
0
ns
3
DQS-in hold time
DQS-in falling edge to CK rising-setup
time
t
WPREH
0.25
0.25
0.25
t
CK
t
DSS
0.2
0.2
0.2
t
CK
DQS-in falling edge to CK rising hold time
t
DSH
0.2
0.2
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
0.35
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-in cycle time
t
DSC
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Address and Control Input setup time
t
IS
1.1
0.9
0.9
ns
Address and Control Input hold time
t
IH
1.1
0.9
0.9
ns
Mode register set cycle time
t
MRD
16
15
15
ns
DQ & DM setup time to DQS
t
DS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
t
DH
0.6
0.5
0.5
ns
DQ & DM input pulse width
t
DIPW
2
1.75
1.75
ns
Power down exit time
t
PDEX
10
10
10
ns
Exit self refresh to write command
t
XSW
116
95
ns
Exit self refresh to bank active command
t
XSA
80
75
75
ns
Exit self refresh to read command
t
XSR
200
200
200
Cycle
Refresh interval time
T
REF
7.8
7.8
7.8
us
1
Output DQS valid window
T
QH
0.35
0.35
0.35
t
CK
DQS write postamble time
Notes :
T
WPST
0.25
0.25
0.25
t
CK
4
1. Maximum burst refresh of 8.
2. t
HZQ
transitions occurs in the same assess time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on t
DQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDD32M72B18RWP-10A | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72D18RPW | DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72B9 | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13A | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13B | DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDD32M72B18RWP-10A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K Ref., 184Pin-DIMM with PLL & Register |
| HDD32M72B9 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13A | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-13B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
| HDD32M72B9-16B | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM |
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