參數(shù)資料
型號(hào)： HDD16M64F8-10A
廠商： Hanbit Electronics Co.,Ltd.
英文描述： DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
中文描述： DDR SDRAM內(nèi)存模塊128Mbyte（16Mx64bit）根據(jù)on16Mx8，4Banks，4K的參考。，SMM的，
文件頁(yè)數(shù)： 8/11頁(yè)
文件大?。?/td> 147K
代理商： HDD16M64F8-10A
HANBit
HDD16M64F8
URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 1.0(August.2002)
Clock high level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
DQS-out access time from CK/CK
t
DQSCK
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
t
AC
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
t
DQSQ
-
+0.6
-
+0.5
-
+0.5
ns
Read Preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Read Postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
Data out high impedence time from CK-
/CK
t
HZQ
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
2
CK to valid DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
0
0
ns
3
DQS-in hold time
t
WPREH
0.25
0.25
0.25
t
CK
DQS-in falling edge to CK rising-setup
time
t
DSS
0.2
0.2
0.2
t
CK
DQS-in falling edge to CK rising hold
time
t
DSH
0.2
0.2
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
0.35
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-in cycle time
t
DSC
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Address and Control Input setup time
t
IS
1.1
0.9
0.9
ns
Address and Control Input hold time
t
IH
1.1
0.9
0.9
ns
Mode register set cycle time
t
MRD
16
15
15
ns
DQ & DM setup time to DQS
t
DS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
t
DH
0.6
0.5
0.5
ns
DQ & DM input pulse width
t
DIPW
2
1.75
1.75
ns
Power down exit time
t
PDEX
10
10
10
ns
Exit self refresh to write command
t
XSW
116
95
ns
Exit self refresh to bank active
command
t
XSA
80
75
75
ns
Exit self refresh to read command
t
XSR
200
200
200
Cycle
Refresh interval time
T
REF
15.6
15.6
15.6
us
1
Output DQS valid window
T
QH
0.35
0.35
0.35
t
CK
DQS write postamble time
Notes :
T
WPST
0.25
0.25
0.25
t
CK
4
1. Maximum burst refresh of 8.
2. t
HZQ
transitions occurs in the same assess time windows as valid data transitions. These parameters
are not
referenced to a specific voltage level, but specify when the device output is no longer driving.
The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on t
DQSS
.
3.
相關(guān)PDF資料
PDF描述
HDD16M64F8-13A DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
HDD16M64F8-13B DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
HDD16M72D9RPW DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register
HDD16M72D9RPW-10A DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register
HDD16M72D9RPW-13A DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDD16M64F8-13A 制造商:HANBIT 制造商全稱(chēng):Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
HDD16M64F8-13B 制造商:HANBIT 制造商全稱(chēng):Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,
HDD16M72D9RPW 制造商:HANBIT 制造商全稱(chēng):Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register
HDD16M72D9RPW-10A 制造商:HANBIT 制造商全稱(chēng):Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register
HDD16M72D9RPW-13A 制造商:HANBIT 制造商全稱(chēng):Hanbit Electronics Co.,Ltd 功能描述:DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register
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