參數(shù)資料
型號: HD49235FS
廠商: Hitachi,Ltd.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processor for CD
中文描述: 數(shù)字信號處理器的CD
文件頁數(shù): 32/41頁
文件大小: 192K
代理商: HD49235FS
HD49235FS
Rev.2, Aug. 1995, page 32 of 41
Normal Mode:
The MON output pin is held high. The PWM pin outputs a rectangular wave with a
duty cycle that depends on the length of four cycles of the sync signal reproduced from the disc (four
frames). See the PWM output duty cycle characteristic in figure 19. The MSTOP pin outputs a phase
error signal obtained by comparing the phase of a signal obtained by prescaling the sync signal by a
factor of four (to give a cycle length of four frames) with the phase of an internal reference signal. See
the MSTOP output duty cycle characteristic in figure 20.
3. Rotate Mode
The MON and PWM outputs are held high. The MSTOP pin outputs a square wave with a 50% duty
cycle. This mode is used to force the disc motor to rotate.
4. Kick Mode
The MON output pin is held high. The MSTOP pin outputs a square wave with a 50% duty cycle. The
PWM pin outputs a rectangular wave with a duty cycle that can be set to any value from 0 to 100% in
128 steps by setting bits KICK7 to KICK1 in microprocessor command register D.
5. Brake Mode
The MON output is held high. The MSTOP pin outputs a square wave with a 50% duty cycle. The
PWM output is held low. This mode is used to force the disc motor to rotate in reverse. In brake mode,
the interval between edges of the EFM signal is measured. If the interval is 32 T or more (T = 1/4.3218
MHz) the SENS output is driven low and the PW64 output is driven low. These outputs can be
monitored to find if braking has been effective.
6. Access (ACS) Mode
Operation is the same as in the starting submode of play mode. This mode is used in track access.
7. Start mode
Operation is the same as in the starting submode of play mode.
8. Normal Mode
Operation is the same as in the normal submode of play mode.
100
75
25
0
64T
32T
32T
64T
6 dB
0 dB
+6 dB
6 dB
0 dB
+6 dB
Center: 588 T (1 frame)
×
4 = 2352 T
7 bit 128 step
PWM duty cycle
(%)
Figure 19 Duty Cycle Characteristic of PWM Output (Speed Error) in CLV Normal Mode
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