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參數(shù)資料
| 型號(hào)： | HD49235FS |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processor for CD |
| 中文描述： | 數(shù)字信號(hào)處理器的CD |
| 文件頁數(shù)： | 24/41頁 |
| 文件大?。?/td> | 192K |
| 代理商： | HD49235FS |
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HD49235FS
Rev.2, Aug. 1995, page 24 of 41
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
DATA
CLK
XLT
Figure 12 Microprocessor Interface Timing
2. Microprocessor Commands
These commands are summarized in the microprocessor command tables. Further details and notes are
given below.
a. Mode Selections (Register 8)
ROM:
This bit controls whether or not interpolation is performed on audio data output from DAS.
When ROM = 0, interpolation is performed (for audio applications).
When ROM = 1, interpolation is not performed (for CD-ROM applications).
ROMEF:
When ROM = 1 (for CD-ROM applications), the upper and lower C2 flag data is output in
two 8-bit segments. ROMEF selects which is output first: the upper or lower data.
When ROMEF = 0, the lower data is output first.
When ROMEF = 1, the upper data is output first.
DOOFF:
This bit switches the digital audio interface output from pin 17 (BIDAT) on or off.
When DOOFF = 0, a signal is output.
When DOOFF = 1, the BIDAT pin is in the high-impedance state.
SUBCO:
This bit selects whether to insert subcode data in the DAS output on the DAC output interface
(MPX, CKX, DAS) in 48fs clock mode (when microprocessor command bit SLTSW is 0).
When SUBCO = 0, subcode data is not inserted.
When SUBCO = 1, subcode data is inserted.
SLTSW:
This bit selects 48fs clock mode or 64fs clock mode for the DAS output.
When SLTSW = 0, DAS data is output in 48fs clock mode.
When SLTSW = 1, DAS data is output in 64fs clock mode.
DCOND:
This bit selects the condition for switching from the analog PLL to the digital PLL when a
defect is detected, in terms of the width of the defect detection signal input at the DEFCT pin (pin 69).
When DCOND = 0, the width must be at least four frames.
When DCOND = 1, the width must be at least eight frames.
Analog
Digital
Analog
Set by DWIDTH
Set by DCOND
PLL
DEFCT (defect
detection signal)
Figure 13 PLL Modes when a Defect is Detected
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