![](http://datasheet.mmic.net.cn/280000/HD4074459_datasheet_16064711/HD4074459_10.png)
HD404459 Series
10
$000
$003
PMRA $004
SMRA $005
SRL $006
SRU $007
TMA $008
TMB1 $009
TRBL/TWBL $00A
TRBU/TWBU $00B
MIS $00C
TMC1 $00D
TRCL/TWCL$00E
TRCU/TWCU $00F
TMD1 $010
TRDL/TWDL $011
TRDU/TWDU $012
TMB2 $013
TMC2 $014
TMD2 $015
CCR $016
CER $017
WSR $018
$020
$023
PMRB $024
PMRC $025
ESR1 $026
ESR2 $027
SMRB $028
SSR1 $029
SSR2 $02A
DCD0 $02C
DCD1 $02D
DCD2 $02E
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
DCR4 $034
DCR5 $035
DCR6 $036
DCR7 $037
DCR8 $038
DCR9 $039
$03F
Not used
Interrupt control bits area
R4
2
/SI
R4
3
/SO
R4
1
/
SCK
Serial transmit clock speed selection
Serial data register (lower digit)
Serial data register (upper digit)
Clock source selection (timer A)
Clock source selection (timer B)
Timer B register (lower digit)
Timer B register (upper digit)
SO PMOS control
Clock source selection (timer C)
Timer C register (lower digit)
Timer C register (upper digit)
Clock source selection (timer D)
Timer D register (lower digit)
Timer D register (upper digit)
Not used
Timer-A/timer-base
Auto-reload on/off
Pull-up MOS control
Auto-reload on/off
Auto-reload on/off
Interrupt frame period selection
Timer B output mode selection
Timer C output mode selection
Timer D output mode selection
Internal reference voltage level selection
Reference power supply selection
Voltage comparison result
WU
7
WU
6
enable
WU
5
to
WU
4
enable
WU
3
to
WU
0
enable
R0
3
/INT
3
Not used
R0
2
/INT
2
D
11
/
STOPC
R0
1
/
INT
1
R4
0
/EVND
INT
2
detection edge selection
Not used
R0
0
/
INT
0
R3
3
/
EVNB
INT
3
detection edge selection
EVND detection edge selection
Not used
SO output level control in idle states
32-kHz oscillation sampling selection
Serial clock source selection
Not used
32-kHz oscillation stop
Not used
32-kHz oscillation division ratio selection
Not used
OSC division ratio selection
Port D3 DCR
Port D7 DCR
Not used
Port D2 DCR
Port D6 DCR
Not used
Port D1 DCR
Port D5 DCR
Port D9 DCR
Port D0 DCR
Port D4 DCR
Port D8 DCR
Port R0
3
DCR
Port R1
3
DCR
Port R2
3
DCR
Port R3
3
DCR
Port R4
3
DCR
Port R5
3
DCR
Port R6
3
DCR
Port R7
3
DCR
Port R8
3
DCR
Port R0
2
DCR
Port R1
2
DCR
Port R2
2
DCR
Port R3
2
DCR
Port R4
2
DCR
Port R5
2
DCR
Port R6
2
DCR
Port R7
2
DCR
Port R8
2
DCR
Port R9
2
DCR
Port R0
1
DCR
Port R1
1
DCR
Port R2
1
DCR
Port R3
1
DCR
Port R4
1
DCR
Port R5
1
DCR
Port R6
1
DCR
Port R7
1
DCR
Port R8
1
DCR
Port R9
1
DCR
Port R0
0
DCR
Port R1
0
DCR
Port R2
0
DCR
Port R3
0
DCR
Port R4
0
DCR
Port R5
0
DCR
Port R6
0
DCR
Port R7
0
DCR
Port R8
0
DCR
Port R9
0
DCR
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
COMP
0
to COMP
3
selection
Register flag area
Bit 3
Bit 2
Bit 1
Bit 0
Input capture selection
Figure 5 Special Function Register Area