參數(shù)資料
型號(hào): HB52F169EN
廠商: Hitachi,Ltd.
英文描述: 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
中文描述: 64 MB的無緩沖SDRAM的內(nèi)存(64 MB的未緩沖同步的DRAM內(nèi)存)
文件頁數(shù): 45/71頁
文件大?。?/td> 906K
代理商: HB52F169EN
HB52F88EM-75F, HB52F89EM-75F, HB52F168EN-75F, HB52F169EN-
45
2. Single write:
A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address (BA) specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
Auto Precharge
Read with auto-precharge:
In this operation, since precharge is automatically performed after completing
a read operation, a precharge command need not be executed after each read operation. The command exe-
cuted for the same bank after the execution of this command must be the bank active (ACTV) command. In
addition, an interval defined by l
APR
is required before execution of the next command.
Burst Read (Burst Length = 4)
Write with auto-precharge:
In this operation, since precharge is automatically performed after completing
a burst write or single write operation, a precharge command need not be executed after each write operation.
The command executed for the same bank after the execution of this command must be the bank active
(ACTV) command. In addition, an interval of l
APW
is required between the final valid data input and input
of next command.
CE latency
3
2
Precharge start cycle
2 cycle before the final data is output
1 cycle before the final data is output
WRIT
CK
Command
Din
ACTV
Row
Column
in 0
Address
t
RCD
CLK
lAPR
CL=3 Command
DQ (input)
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of t
RAS
(l
RAS
) is required between previous active (ACTV) command and internal precharge " ".
lRAS
ACTV
READ A
ACTV
out3
out2
out1
out0
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