參數(shù)資料
型號(hào): HB52E649EN-B6B
元件分類(lèi): DRAM
英文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁(yè)數(shù): 5/29頁(yè)
文件大?。?/td> 134K
代理商: HB52E649EN-B6B
HB52E648EN/HB52E649EN-A6B/B6B
13
Block Diagram (HB52E649EN)
DQMB0
D1
I/O0
to I/O7
I/O0
to I/O7
DQM
DQ0
to DQ7
DQ8
to DQ15
DQMB1
* D0 to D17: HM5225805
U0: 2-kbit EEPROM
C0 to C17: 0.33
F, C18 to C35: 0.10 F
R0: 10 k
, R1: 47 k
N0 to N17: Network registor 10
R100 to R103: 10
CKE (D9 to D17)
Serial PD
SDA
A0
A1
A2
SA0 SA1 SA2
VCC
CKE1
CKE (D0 to D8)
CKE0
SCL
U0
SDA
SCL
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
3. SDRAM D11 DQMB input is wired to DQMB5
because of the normal SCL line inacitve
R0
8 N0, N1
N4, N5
N6, N7
N8, N9
N10, N11
N12, N13
N14, N15
N16, N17
8
DQMB4
DQ32
to DQ39
DQ40
to DQ47
DQMB5
8
VCC (D0 to D17, U0)
VSS (D0 to D17, U0)
VSS
VCC
C18 to C35
C0 to C17
VSS
R1
RE, CE, W
CS
D6
D5
D0
I/O0
to I/O7
I/O0
to I/O7
DQM
CS
S1
S2
"high" state.
DQMB2
D4
I/O0
to I/O7
I/O0
to I/O7
DQM
DQ16
to DQ23
DQ24
to DQ31
DQMB3
8
DQMB6
DQ48
to DQ55
DQ56
to DQ63
DQMB7
8
CS
D8
D7
D3
I/O0
to I/O7
I/O0
to I/O7
DQM
CS
S0
A0 to A12, BA0, BA1
D15
D14
I/O0
to I/O7
I/O0
to I/O7
DQM
CS
S3
D17
D16
I/O0
to I/O7
I/O0
to I/O7
DQM
CS
D10
I/O0
to I/O7
I/O0
to I/O7
DQM
CS
D2
I/O0
to I/O7
DQM
CB0
to CB7
8
CS
D11
I/O0
to I/O7
DQM
CS
D9
D13
I/O0
to I/O7
I/O0
to I/O7
DQM
CS
D12
R100
R101
CK0
CLK (5 SDRAMs)
CK1
R102
R103
CK2
CLK (4 SDRAMs + 3.3 pF cap)
CK3
WP
N2, N3
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