參數(shù)資料
型號(hào)： HB52E168EN
廠商： Hitachi,Ltd.
英文描述： 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM)
中文描述： 64 MB的無(wú)緩沖SDRAM的內(nèi)存（64MB的未緩沖同步的DRAM內(nèi)存）
文件頁(yè)數(shù)： 28/64頁(yè)
文件大小： 2741K
代理商： HB52E168EN
HB52E88EM-F, HB52E89EM-F, HB52E168EN-F, HB52E169EN-F
28
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]:
The SDRAM module has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
DQMB Truth Table
Note: H: V
IH
. m L: V
IL
.
×
: V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
The SDRAM module can mask input/output data by means of DQMB.
During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the
other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is
held (the new data is not written). Desired data can be masked during burst read or burst write by setting
DQMB. For details, refer to the DQMB control section of the SDRAM module operating instructions.
CKE Truth Table
Note: H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
Clock suspend mode entry:
The SDRAM module enters clock suspend mode from active mode by setting
CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown
below.
Command
Write enable/output enable
Write inhibit/output disable
Symbol
ENB
MASK
CKE
n - 1
H
H
DQMB
L
H
n
×
×
Current state
Active
Any
Clock suspend
Idle
Idle
Idle
Command
Clock suspend mode entry
Clock suspend
Clock suspend mode exit
Auto-refresh command (REF)
Self-refresh entry (SELF)
Power down entry
CKE
n - 1
H
L
L
H
H
H
H
L
L
L
L
S
H
×
×
L
L
L
H
L
H
L
H
RE
×
×
×
L
L
H
×
H
×
H
×
CE
×
×
×
L
L
H
×
H
×
H
×
W
×
×
×
H
H
H
×
H
×
H
×
Address
×
×
×
×
×
×
×
×
×
×
×
n
L
L
H
H
L
L
L
H
H
H
H
Self refresh
Self refresh exit (SELFX)
Power down
Power down exit
相關(guān)PDF資料
PDF描述
HB52E169EN 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM)
HB52E88EM 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM)
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