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2
G
Truth Table
(Note 2)
Note 2:
A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA, LEBA, CLKBA, and CEBA.
Note 3:
Output level before the indicated steady state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
Note 4:
Output level before the indicated steady-state input conditions
were established.
Connection Diagram
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Number in front of each pin indicates word.
Inputs
Output
Mode
CEAB OEAB LEAB CLKAB A
B
X
H
X
X
X
Z
Latched
L
L
L
H
X B
0
(Note 3)
storage
L
L
L
L
X B
0
(Note 4)
of A data
X
L
H
X
L
L
Transparent
X
L
H
X
H
H
L
L
L
↑
L
L
Clocked
L
L
L
↑
H
H
storage
of A data
H
L
L
X
X B
0
(Note 4) Clock inhibit
Pin Names
Description
OEAB
A-to-B Output Enable
(Active LOW) (LVTTL Level)
OEBA
B-to-A Output Enable
(Active LOW) (LVTTL Level)
CEAB
A-to-B Clock/LE Enable
(Active LOW) (LVTTL Level)
CEBA
B-to-A Clock/LE Enable
(Active LOW) (LVTTL Level)
LEAB
A-to-B Latch Enable
(Transparent HIGH) (LVTTL Level)
LEBA
B-to-A Latch Enable
(Transparent HIGH) (LVTTL Level)
V
REF
GTLP Input Threshold
Reference Voltage
CLKAB
A-to-B Clock (LVTTL Level)
CLKBA
B-to-A Clock (LVTTL Level)
A
1
–
A
18
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
1
–
B
18
B-to-A Data Inputs or
A-to-B Open Drain Outputs
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1A
2
1A
4
1A
6
1A
8
1A
10
1A
12
1A
14
1A
16
1A
18
1A
1
1A
3
1A
5
1A
7
1A
9
1A
11
1A
13
1A
15
1A
17
1OEAB 1CLKAB
1LEAB
V
CC
GND
GND
GND
V
CC
1OEBA
1LEBA 1CLKBA
1B
2
1B
4
1B
6
1B
8
1B
10
1B
12
1B
14
1B
16
1B
18
1B
1
1B
3
1B
5
1B
7
1B
9
1B
11
1B
13
1B
15
1B
17
1CEAB
V
CC
GND
GND
GND
V
REF
1CEBA
2A
2
2A
4
2A
6
2A
8
2A
10
2A
12
2A
14
2A
16
2A
18
2A
1
2A
3
2A
5
2A
7
2A
9
2A
11
2A
13
2A
15
2A
17
2OEAB 2CLKAB
2LEAB
V
CC
GND
GND
GND
V
CC
2OEBA
2LEBA 2CLKBA
2B
2
2B
4
2B
6
2B
8
2B
10
2B
12
2B
14
2B
16
2B
18
2B
1
2B
3
2B
5
2B
7
2B
9
2B
11
2B
13
2B
15
2B
17
2CEAB
V
CC
GND
GND
GND
V
REF
2CEBA