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參數(shù)資料
| 型號： | GTL2002D |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 電壓/頻率轉(zhuǎn)換 |
| 英文描述： | 2-bit bidirectional low voltage translator |
| 封裝： | GTL2002D/DG<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<Always Pb-free,;GTL2002D<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<week 5, 2 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大小： | 129K |
| 代理商： | GTL2002D |
GTL2002_7
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 2 July 2009
5 of 22
NXP Semiconductors
GTL2002
2-bit bidirectional low voltage translator
8.
Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side V
CC
through a pull-up resistor (typically 200 k
). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to V
CC
). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 k
resistor
to a 3.3 V to 5.5 V V
CC
supply and SREF is set between 1.0 V to (V
CC
1.5 V), the output
of each Sn has a maximum output voltage equal to SREF and the output of each Dn has
a maximum output voltage equal to V
CC
.
Typical bidirectional voltage translation.
Fig 6.
Bidirectional translation to multiple higher voltage levels such as an I
2
C-bus
application
GREF
DREF
002aac060
D1
D2
200 k
CHIPSET I/O
V
CC
5 V
totem pole or
open-drain I/O
GND
SREF
S1
S2
increase bit size
by using 10-bit GTL2010
or 22-bit GTL2000
D3
D4
CHIPSET I/O
V
CC
D5
Dn
3.3 V
S3
S4
S5
Sn
CPU I/O
V
CORE
1.8 V
1.5 V
1.2 V
1.0 V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GTL2002D,112 | 功能描述:轉(zhuǎn)換 - 電壓電平 2-BIT GTL VOLTAGE RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2002D,118 | 功能描述:轉(zhuǎn)換 - 電壓電平 2-BIT GTL VOLTAGE CLAMP TRANS RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2002D/DG,118 | 功能描述:轉(zhuǎn)換 - 電壓電平 Voltage Translator 8-Pin RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2002D/G-T | 功能描述:IC XLATR 2BIT BI-DIREC OD 8-SOIC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類型:CMOS 輸出類型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設(shè)備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| GTL2002D112 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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