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| 型號： | GS9090ACNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9090A GenLINX-R III 270Mb/s Deserializer for SDI |
| 中文描述： | GS9090A GenLINX - R的第三270Mb / s的SDI解串器 |
| 文件頁數(shù)： | 9/69頁 |
| 文件大?。?/td> | 687K |
| 代理商： | GS9090ACNE3 |
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GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
9 of 69
23, 25, 26, 27
STAT[0:3]
Synchronous
with PCLK or
RD_CLK
Output
MULTI FUNCTION I/O PORT
Signal levels are LVCMOS / LVTTL compatible.
Programmable multi-function outputs. By programming the bits is the
IO_CONFIG register, each pin can output one of the following signals:
H
V
F
FIFO_LD
ANC_DETECT
EDH_DETECT
FIFO_FULL
FIFO_EMPTY
These pins are set to certain default values depending on the
configuration of the device and the internal FIFO mode selected. See
Programmable Multi-Function Outputs on page 55
for details.
24, 28, 42
IO_GND
Non
Synchronous
Input
Power
Ground connection for digital I/O. Connect to GND.
30
RD_CLK
–
Input
FIFO READ CLOCK
Signal levels are LVCMOS / LVTTL compatible.
The application layer clocks the parallel data out of the FIFO on the
rising edge of RD_CLK.
31
RD_RESET
Synchronous
with RD_CLK
Input
FIFO READ RESET
Signal levels are LVCMOS / LVTTL compatible.
Valid input only when the device is in SMPTE mode (SMPTE_BYPASS
= HIGH and DVB-ASI = LOW), and the internal FIFO is configured for
video mode (
Video Mode on page 45
).
A HIGH to LOW transition will reset the FIFO pointer to address zero of
the memory.
32 - 41
DOUT[0:9]
Synchronous
with RD_CLK
or PCLK
Output
PARALLEL VIDEO DATA BUS
Signal levels are LVCMOS / LVTTL compatible.
When the internal FIFO is enabled and configured for either video
mode or DVB-ASI mode, parallel data will be clocked out of the device
on the rising edge of RD_CLK.
When the internal FIFO is in bypass mode, parallel data will be clocked
out of the device on the rising edge of PCLK.
DOUT9 is the MSB and DOUT0 is the LSB.
44
PCLK
–
Output
PIXEL CLOCK OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
27MHz parallel clock output.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9090 | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| GS9090-CNE3 | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| GS9092A | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092ACNE3 | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9090B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Deserializer for SDI |
| GS9090B_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Deserializer for SDI |
| GS9090BCNE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS9090BCNTE3 | 制造商:Semtech Corporation 功能描述:270Mb/s Receiver for SDI & ASI |
| GS9090CNE3 | 制造商:Gennum Corporation 功能描述: |
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