參數(shù)資料
型號: GS9090ACNE3
廠商: Gennum Corporation
英文描述: GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述: GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁數(shù): 14/69頁
文件大?。?/td> 687K
代理商: GS9090ACNE3
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
14 of 69
Asynchronous Lock Time (LOCKED
signal set HIGH)
t
LOCK
Input jitter of 0.2UI,
No data to non-SMPTE,
SMPTE_BYPASS = LOW
DVB_ASI = LOW,
at 25°C
165
us
1
Serial Digital Input
Serial Input Data Rate
DR
SDI
270
Mb/s
Serial Input Jitter Tolerance
IJT
0.5
UI
2
Differential Input Voltage Range
BUFF_VDD = 1.8V
200
800
1700
mV
p-p
BUFF_VDD = 3.3V
100
800
2200
mV
p-p
Parallel Output
Parallel Output Clock Frequency
f
PCLK
27
MHz
Parallel Output Clock Duty Cycle
DC
PCLK
40
60
%
Variation of Parallel Output Clock
(from 27MHz)
Device Unlocked
T
A
= -20°C to +85°C
IO_VDD = 1.8V
-7.5
+7.5
%
3
Output Data Hold Time
t
OH
With 15pF load
3.0
ns
4
Output Delay Time
t
OD
With 15pF load
10.0
ns
4
GSPI
GSPI Input Clock Frequency
f
GSPI
54.0
MHz
GSPI Clock Duty Cycle
DC
GSPI
40
60
%
GSPI Setup Time
t
GS
1.5
ns
GSPI Hold Time
t
GH
1.5
ns
NOTES
1. No signal to signal present, or a switch from another data rate to 270Mb/s.
2. Power supply noise 50mV
pp
at 15kHz, 100kHz, 1MHz sinusoidal modulation.
3. When the serial input to the GS9090A is removed, the PCLK output signal will continue to operate at 27MHz and the internal VCO will
remain at this frequency within +/- 7.5% over the range -20
o
C to +85
o
C.
4. Timing includes the following outputs: DOUT[9:0], STAT[3:0]. When the FIFO is enabled, the outputs are measured with respect to
RD_CLK.
Table 2-3: AC Electrical Characteristics (Continued)
V
DD
= 1.8V, T
A
= 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
Notes
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