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參數(shù)資料
| 型號： | GS9062-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9062 HD-LINX-TM II SD-SDI and DVB-ASI Serializer |
| 中文描述： | GS9062的HD - LINX進程，商標第二SD - SDI和DVB - ASI在內(nèi)串行器 |
| 文件頁數(shù)： | 9/46頁 |
| 文件大?。?/td> | 473K |
| 代理商： | GS9062-CFE3 |
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GS9062 Data Sheet
22209 - 5
May 2005
9 of 46
33, 68
CORE_GND
–
Power
Ground connection for the digital core logic. Connect to digital
GND.
34
F
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all
outgoing TRS signals for the entire period that the F input signal
is HIGH (IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2
and should be set LOW for all lines in field 1 and for all lines in
progressive scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
35
V
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used
for vertical blanking when DETECT_TRS is set LOW. The device
will set the V bit in all outgoing TRS signals for the entire period
that the V input signal is HIGH (IOPROC_EN/DIS must also be
HIGH).
The V signal should be set HIGH for the entire vertical blanking
period and should be set LOW for all lines outside of the vertical
blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
36
H
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active
video data when DETECT_TRS is set LOW. The device will set
the H bit in all outgoing TRS signals for the entire period that the
H input signal is HIGH (IOPROC_EN/DIS must also be HIGH).
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0
h
)
The H signal should be set HIGH for the entire horizontal
blanking period, including the EAV and SAV TRS words, and
LOW otherwise. This is the default setting.
TRS Based Blanking (H_CONFIG = 1
h
)
The H signal should be set HIGH for the entire horizontal
blanking period as indicated by the H bit in the received TRS ID
words, and LOW otherwise.
37, 64
CORE_VDD
–
Power
Power supply connection for the digital core logic. Connect to
+1.8V DC digital.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關PDF資料 |
PDF描述 |
|---|---|
| GS9064-CKD | GS9064 SD SDI Adaptive Cable Equalizer |
| GS9064-CKDE3 | GS9064 SD SDI Adaptive Cable Equalizer |
| GS9064A | GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9074A | GS9074A HD-LINX-R II Adaptive Cable Equalizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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