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參數(shù)資料
| 型號： | GS9023-CFY |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Aluminum Electrolytic Radial Leaded Bi-Polar Capacitor; Capacitance: 100uF; Voltage: 63V; Case Size: 12.5x20 mm; Packaging: Bulk |
| 中文描述： | 嵌入式音頻編解碼器 |
| 文件頁數(shù)： | 7/33頁 |
| 文件大?。?/td> | 301K |
| 代理商： | GS9023-CFY |
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GENNUM CORPORATION
522 - 45 - 05
7
G
DETAILED DESCRIPTION
The GS9023 has two main modes of operation: Multiplex
Mode and Demultiplex Mode. In Multiplex Mode, which is
selected by setting the DEMUX/MUX input pin LOW, digital
audio is embedded into a digital video stream. In
Demultiplex Mode, which is selected by setting the DEMUX/
MUX input pin HIGH, digital audio is extracted from a digital
video stream. Tables 14 and 15 contain Host Interface
Register descriptions for the Multiplex and Demultiplex
Modes respectively.
MULTIPLEX MODE
Video Clock Input
A master video clock must be supplied to the PCLK pin
corresponding to the selected video standard. The
supported video input standards and corresponding clock
frequencies are listed in Table 1.
Video Data Input
The video data DIN[9:0] is clocked into the GS9023 on the
rising edge of PCLK. The video clock frequency must
correspond to the video input standard selected. This is
done via the
“
VSEL
”
bit of Host Interface Register #0h.
When
“
VSEL
”
is LOW, the video input standard is selected
by the VM[2:0] and TRS input pins. When
“
VSEL
”
is HIGH,
the video input standard is selected by the
“
VMOD[2:0]
”
and
“
D2_TRS
”
bits in Host Interface Register #0h. The
supported video input standards are listed in Table 1.
After the user has specified the video input standard via the
VM[2:0] and TRS pins or by setting Host Interface
Register #0h, the GS9023 performs video standard
detection to verify that the input video stream corresponds
to the selected standard. When the selected video input
standard is verified, the
“
VXST
”
bit of Host Interface
Register #0h is set HIGH. The LOCK output pin and the
“
LOCK
”
bit of Host Interface Register #0h are then set
HIGH if at least one of the audio channel enable bits
“
CHACT(4-1)
”
of Host Interface Register #1h is HIGH and
the start of a video frame is detected.
NOTE: The user must ensure that the video input format
correctly corresponds to the video format being provided to
the GS9023.
TABLE 1: Video Input Formats
VIDEO STANDARD
SERIAL DIGITAL
DATA RATE
(Mbps)
PCLK
FREQUENCY
(MHz)
VM[2] or
“
VMOD[2]
”
VM[1] or
“
VMOD[1]
”
VM[0] or
“
VMOD[0]
”
TRS or
“
D2_TRS
”
525/D2 (SMPTE259M)
143
14.3
0
0
0
0
525/D2 (SMPTE244M)
143
14.3
0
0
0
1
525/D1
270
27.0
0
0
1
0
Reserved
-
-
0
0
1
1
525/16:9
360
36.0
0
1
0
0
Reserved
-
-
0
1
0
1
525/4:4:4:4 (System #1)
540
54.0
0
1
1
0
Reserved
-
-
0
1
1
1
625/D2 (with TRS)
177
17.7
1
0
0
0
625/D2 (without TRS)
177
17.7
1
0
0
1
625/D1
270
27.0
1
0
1
0
Reserved
-
-
1
0
1
1
625/16:9
360
36.0
1
1
0
0
Reserved
-
-
1
1
0
1
625/4:4:4:4 (System #2)
540
54.0
1
1
1
0
625/4:2:2P (System #4)
540
54.0
1
1
1
1
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