- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385344 > GS9021ACFU (Gennum Corporation) GENLINX -TM II GS9021A EDH Coprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | GS9021ACFU |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX -TM II GS9021A EDH Coprocessor |
| 中文描述： | GENLINX -商標(biāo)二GS9021A硬腦膜外血腫協(xié)處理器 |
| 文件頁數(shù)： | 16/26頁 |
| 文件大?。?/td> | 245K |
| 代理商： | GS9021ACFU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
19983 - 1
16 of 26
G
If the HOST interface is not going to be used, the best way
to set the related pins is as follows:
HOSTIF_MODE = LOW
CS = HIGH
R/W = HIGH
A/D = DON'T CARE (BUT NOT FLOATING)
P[7:0] = N/C
5.1 I2C Serial Interface
The I2C interface consists of a bi-directional serial data pin
(SDA) and a serial clock input pin (SCL). In addition, 3 input
pins, A[2:0] are provided to assign the chip one of eight
possible I2C addresses (0001A
2
A
1
A
0
).
During an I2C write operation, the first byte written to the
chip (after the device has been addressed) is interpreted
as the starting HOSTIF write table address for the
communication. The next byte is interpreted as data to be
written to the specified address. The address then
automatically increments so that the following bytes are
written to subsequent addresses.
When executing a read operation, a write must be per-
formed first to load the desired starting address. After this,
bytes read from the chip will begin at this address and will
auto-increment. If the read operation is halted and
communication with the chip is later established for another
read, the chip will resume reading at the next HOSTIF
memory address.
In I2C mode, P[7:5] and A/D must be set LOW while R/W
and CS must be set HIGH.
5.2 Parallel Interface
The asynchronous parallel interface consists of an 8-bit
multiplexed address/data bus (P[7:0]), a chip select pin
(CS), a read/write pin (R/W), and an address/data pin (A/D).
The following should be noted when interfacing to the
parallel port:
A) Read/Write cycles via the parallel interface are
completely independent and asynchronous to the
parallel clock PCLKIN.
B) Signals are "strobed" into/out of the parallel port on the
falling edge of the CS signal. Setup and hold times, as
defined in the AC timing tables, are relative to this edge
and must be met (see Figure 8a)
C) The GS9021A drives the P[7:0] bus when the R/W pin is
HIGH and the CS pin is LOW. At all other times, the
P[7:0] port is in a high impedance state. The host
interface enable and disable times are shown in Figure
8b and are specified in the AC timing information. In this
figure, the rising/falling edges of R/W and CS are not
aligned to illustrate that the state of the P[7:0] I/Os is
only a combinatorial function of the R/W and CS pins.
A write cycle to the parallel interface is shown in Figure 8c.
The starting address of the operation is written to the chip
by putting the R/W pin LOW (indicating write) and the A/D
pin high (indicating ADDRESS). At t
0
, the falling edge of CS
strobes in the information. Following this, the A/D line
should be asserted LOW indicating data. The R/W line
remains LOW indicating a write operation and at t
1
the data
is strobed into the device.
A read example follows the write cycle. Note that the read
cycle begins with a write operation to indicate the starting
address. At t
2
, R/W is LOW (indicating write), A/D is HIGH
(indicating address) and P[7:0] represent the starting
address for the read cycle. After sufficient hold time, the
microcontroller releases the P[7:0] bus and the R/W is
asserted HIGH to indicate a read operation. At t
3
, the CS is
asserted low causing the GS9021A to present the required
data on the P[7:0] bus.
If two consecutive data read/write operations are
performed, the device will automatically increment the
address. However, for a completely random-access
operation, the address can be specified prior to every data
read/write operation.
PIN
LOGIC OPR
HOST BIT
SCL
SDA
A[2:0]
PIN
LOGIC OPR
HOST BIT
P[7:0]
A/D
R/W
CS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9022-CPJ | Digital Video Serializer |
| GS9022 | Digital Video Serializer |
| GS9022-CTJ | Digital Video Serializer |
| GS9022ACPJE3 | GENLINXTM GS9022A Digital Video Serializer |
| GS9022ACTJE3 | GENLINXTM GS9022A Digital Video Serializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9021ACFUE3 | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:EDH Co-Processer |
| GS9021-CFU | 制造商:Gennum Corporation 功能描述: |
| GS9021-CTU | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EDH Coprocessor |
| GS9022 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Video Serializer |
| GS9022A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serializer for SDI at 270-360Mb/s with Cable Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。