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參數資料
| 型號： | GS90015BCPJE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX-TM GS9015B Serial Digital Reclocker |
| 中文描述： | GENLINX -商標GS9015B串行數字時鐘恢復器 |
| 文件頁數： | 3/13頁 |
| 文件大?。?/td> | 119K |
| 代理商： | GS90015BCPJE3 |
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Commutating diodes in the charge pump keep the output
leakage current extremely low, minimizing VCO frequency
drift.
FORNEWDESGNS
The VCO is implemented using a current-controlled
multivibrator, designed to deliver good stability, low phase
noise and wide operating frequency capability. The frequency
range is design-limited to ±10% about the oscillator centre
frequency.
The GS9015B Reclocking Receiver is a bipolar integrated
circuit containing circuitry necessary to re-clock and
regenerate the NRZI serial data stream.
Packaged in a 28 pin PLCC, the receiver operates from a
single five volt supply at data rates to 400 Mb/s. Typical power
consumption is 330 mW. Typical output jitter is ±100 ps
at 270 Mb/s.
Serial Digital signals are applied to digital inputs DDI and DDI
(pins 5,6).
tD
SERIAL
DATA OUT
(SD0)
50%
SERIAL
CLOCK OUT
(SCK)
tD
50%
Phase Locked Loop
The phase comparator itself compares the position of
transitions in the incoming signal with the phase of the local
oscillator (VCO). The error-correcting output signals are fed
to the charge pump in the form of short pulses. The charge
pump converts these pulses into a “charge packet” which is
accurately proportional to the system phase error.
The charge packet is then integrated by the second-order
loop filter to produce a control voltage for the VCO.
During periods when there are no transitions in the signal, the
loop filter voltage is required to hold precisely at its last value
so that the VCO does not drift significantly between corrections.
Fig.1 Waveforms
VCO Centre Frequency Selection
The centre frequency of the VCO is set by one of four external
current reference resistors (RVCO0-RVCO3) connected to
pins 13,14,15 or 17. These are selected by two logic inputs
SS0 and SS1 (pins 20, 21) through a 2:4 decoder according
to the following truth table.
SS1
SS0 Resistor Selected
0
0
RVCO0 (13)
0
1
RVCO1 (14)
1
0
RVCO2 (15)
1
1
RVCO3 (17)
As an alternative, the GS9010A Automatic Tuning Sub-system
and the GS9000B or GS9000S Decoder may be used in
conjunction with the GS9015B to obtain adjustment free and
automatic standard select operation (see Figure17).
With the VCO operating at twice the clock frequency, a clock
phase which is centred on the eye of the locked signal is used
to latch the incoming data, thus maximising immunity to
jitter-induced errors. The alternate phase is used to latch the
output re-clocked data SDO and SDO (pins 25, 24). The true
and inverse clock signals themselves are available from the
SCO and SCO pins 23 and 22.
GS9015B Reclocking Receiver - Detailed Device Description
相關PDF資料 |
PDF描述 |
|---|---|
| GS9015BCPJ | GENLINX-TM GS9015B Serial Digital Reclocker |
| GS9015BCTJ | GENLINX-TM GS9015B Serial Digital Reclocker |
| GS9002ACPM | GENLINX-TM GS9002A Serial Digital Encoder |
| GS9002ACPME3 | GENLINX-TM GS9002A Serial Digital Encoder |
| GS9004D | GENLINX-TM GS9004D Serial Digital Cable Equalizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9001-CQM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9001-CQME3 | 制造商:Semtech Corporation 功能描述:EDH Co-Processer |
| GS9001-CTM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9001-CTME3 | 制造商:Semtech Corporation 功能描述:EDH Co-Processer |
| GS9001-QCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMPTE |
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