參數(shù)資料
型號(hào)： GS881E36BT-300I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
中文描述： 256K X 36 CACHE SRAM, 5 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 21/39頁(yè)
文件大?。?/td> 815K
代理商： GS881E36BT-300I
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Rev: 1.04a 3/2009
28/39
2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
1
0
1
0
1
0
1
0
1
0
1
10
0
1
11
1
相關(guān)PDF資料
PDF描述
GS881E36BT-333 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS881E36BGT-250T 256K X 36 CACHE SRAM, 5.5 ns, PQFP100
GS882Z36BD-166 256K X 36 ZBT SRAM, 7 ns, PBGA165
GS882Z36BGD-166I 256K X 36 ZBT SRAM, 7 ns, PBGA165
GS882Z36BGD-225T 256K X 36 ZBT SRAM, 6 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS881E36BT-333 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS881E36BT-333I 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS881E36CD-300 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 9MBIT 256KX36 5NS/2.5NS 165FPBGA - Trays
GS881E36CD-300I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 9MBIT 256KX36 5NS/2.5NS 165FPBGA - Trays
GS881E36CD-333 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 9MBIT 256KX36 4.5NS/2.5NS 165FPBGA - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*