參數(shù)資料
型號(hào)： GS88136T-80I
英文描述： x36 Fast Synchronous SRAM
中文描述： x36快速同步SRAM
文件頁(yè)數(shù)： 7/33頁(yè)
文件大?。?/td> 616K
代理商： GS88136T-80I
Rev: 1.10 7/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
7/33
2000, Giga Semconductor, Inc.
Preliminary
GS88118/36T-11/11.5/100/80/66
Mode Pin Functions
Note:
There are pull up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Mode Name
Pin Name
State
L
H or NC
L
H or NC
L or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Check for Odd Parity
Check for Even Parity
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
H
ByteSafe Data Parity Control
DP
L
H or NC
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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