參數(shù)資料
型號(hào)： GS88136T-66
英文描述： x36 Fast Synchronous SRAM
中文描述： x36快速同步SRAM
文件頁(yè)數(shù)： 1/33頁(yè)
文件大?。?/td> 616K
代理商： GS88136T-66
Rev: 1.10 7/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
1/33
2000, Giga Semconductor, Inc.
Preliminary
GS88118/36T-11/11.5/100/80/66
512K x 18, 256K x 36 ByteSafe
8Mb Sync Burst SRAMs
100 MHz–66 MHz
3.3 V V
DD
3.3 V and 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipelined operation
Single Cycle Deselect (SCD) Operation
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip write parity checking; even or odd selectable
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Common data inputs and data outputs
Clock Control, registered, address, data, and control
Internal self-timed write cycle
Automatic power-down for portable applications
100-lead TQFP package
-11
-11.5
Pipeline
3-1-1-1
t
KQ
I
DD
Flow
Through
2-1-1-1
I
DD
Functional Description
Applications
The GS88118//36T is a 9,437,184-bit high performance synchronous
SRAMwith a 2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in synchronous
SRAMapplications, ranging fromDSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAMin Flow Through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAMin Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118//36T is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the byte write control inputs.
ByteSafe Parity Functions
The GS88118/36T features ByteSafe data security functions. See
detailed discussion following.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (high) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS88118//36T operates on a 3.3 V power supply, and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise fromthe internal
circuit.
-100
10 ns
4.0 ns
225 mA
-80
-66
15 ns
5.0 ns
185 mA
tCycle
10 ns
4.0 ns
225 mA
10 ns
4.0 ns
225 mA
12.5 ns
4.5 ns
200 mA
t
KQ
tCycle
11 ns
15 ns
180 mA
11.5 ns
15 ns
180 mA
12 ns
15 ns
180 mA
14 ns
15 ns
175 mA
18 ns
20 ns
165 mA
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GS88136T-80 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
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