參數(shù)資料
型號: GS88118
廠商: GSI TECHNOLOGY
英文描述: 8Mb(512K x 18Bit) ByteSafe Synchronous Burst SRAM(8M位(512K x 18位)ByteSafe同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器))
中文描述: 8MB的(為512k × 18位)ByteSafe同步突發(fā)靜態(tài)存儲器(800萬位(為512k × 18位)ByteSafe同步靜態(tài)隨機存儲器(帶2位脈沖地址計數(shù)器))
文件頁數(shù): 7/33頁
文件大?。?/td> 463K
代理商: GS88118
Rev: 1.11 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
7/33
2000, Giga Semconductor, Inc.
Preliminary
GS88118/36T-11/11.5/100/80/66
This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow
Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are
reported one clock cycle later. (See
Write Parity Error Output Timing Diagram
.) The Data Parity Mode (DP) pin must be tied
high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data.
Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a
parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
Write Parity Error Output Timing Diagram
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
L
H or NC
L
H or NC
L or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Check for Odd Parity
Check for Even Parity
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
H
ByteSafe Data Parity Control
DP
L
H or NC
CK
D In A
D In B
D In C
D In D
D In E
tKQ
tLZ
DQ
QE
F
P
tKQ
tLZ
DQ
QE
D In A
D In B
D In C
D In D
D In E
Err A
Err A
Err C
Err C
tHZ
tKQX
tHZ
tKQX
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