參數(shù)資料
型號(hào)： GS880Z18CT-250IVT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 18 ZBT SRAM, QFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 5/24頁(yè)
文件大小： 804K
代理商： GS880Z18CT-250IVT
GS880Z18/32/36CT-xxxV
Rev: 1.02a 12/2010
13/24
2010, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tZZR
tZZH
tZZS
tKL
tKH
tKC
CK
ZZ
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
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