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參數(shù)資料
| 型號： | GS8170DW72AC-350 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| 中文描述： | 256K X 72 STANDARD SRAM, 1.6 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 766K |
| 代理商： | GS8170DW72AC-350 |
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GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
19/32
2003, GSI Technology
AC Electrical Characteristics
Parameter
Symbol
-350
-333
-300
-250
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Clock Cycle Time
tKHKH
2.86
—
3.0
—
3.3
—
4.0
—
ns
—
Clock High Time
tKHKL
1.0
—
1.2
—
1.3
—
1.6
—
ns
—
Clock Low Time
tKLKH
1.0
—
1.2
—
1.3
—
1.6
—
ns
—
Clock High to Echo Clock Low-Z
tKHCX1
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Clock High to Echo Clock High
tKHCH
—
1.7
—
1.8
1.8
—
2.1
ns
—
Clock Low to Echo Clock Low
tKLCL
—
1.7
—
1.8
1.8
—
2.1
ns
Clock High to Echo Clock High-Z
tKHCZ
—
1.7
—
1.8
1.8
—
2.1
ns
1, 2
Clock High to Output Low-Z
tKHQX1
0.5
—
0.5
—
0.5
—
0.5
—
ns
1
Clock High to Output Valid
tKHQV
—
1.7
—
1.8
1.8
—
2.1
ns
—
Clock High to Output Invalid
tKHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
—
Clock High to Output High-Z
tKHQZ
—
1.7
—
1.8
1.8
—
2.1
ns
1
Echo Clock High to Output Valid
tCHQV
—
0.35
—
0.35
—
0.38
—
0.45
ns
2
Echo Clock High to Output Invalid
tCHQX
–0.35
—
–0.35
—
–0.38
—
–0.45
—
ns
2
Address Valid to Clock High
tAVKH
0.4
—
0.6
—
0.7
—
0.8
—
ns
—
Clock High to Address Don’t Care
tKHAX
0.4
—
0.4
—
0.4
—
0.5
—
ns
—
Enable Valid to Clock High
tEVKH
0.4
—
0.6
—
0.7
—
0.8
—
ns
—
Clock High to Enable Don’t Care
tKHEX
0.4
—
0.4
—
0.4
—
0.5
—
ns
—
Write Valid to Clock High
tWVKH
0.4
—
0.6
—
0.7
—
0.8
—
ns
—
Clock High to Write Don’t Care
tKHWX
0.4
—
0.4
—
0.4
—
0.5
—
ns
—
Byte Write Valid to Clock High
tBVKH
0.4
—
0.6
—
0.7
—
0.8
—
ns
—
Clock High to Byte Write Don’t Care
tKHBX
0.4
—
0.4
—
0.4
—
0.5
—
ns
—
Data In Valid to Clock High
tDVKH
0.4
—
0.5
—
0.5
—
0.5
—
ns
—
Clock High to Data In Don’t Care
tKHDX
0.4
—
0.4
—
0.4
—
0.5
—
ns
—
ADV Valid to Clock High
tadvVKH
0.4
—
0.6
—
0.7
—
0.8
—
ns
—
Clock High to ADV Don’t Care
tKHadvX
0.4
—
0.4
—
0.4
—
0.5
—
ns
—
Notes:
1.
2.
3.
Measured at 100 mV from steady state. Not 100% tested.
Guaranteed by design. Not 100% tested.
For any specific temperature and voltage tKHCZ < tKHCX1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8170DW72AC-350I | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW72AGC-250 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW72AGC-250I | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW72AGC-300 | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| GS8170DW72AGC-300I | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8170DW72AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays |
| GS8170DW72AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays |
| GS8170DW72AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays |
| GS8170DW72AGC-300 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays |
| GS8170DW72AGC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays |
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