參數(shù)資料
型號: GS8170DW36AC-250
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
中文描述: 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 7/32頁
文件大?。?/td> 766K
代理商: GS8170DW36AC-250
GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
7/32
2003, GSI Technology
Two Byte Write Control Example with Double Late Write SigmaRAM
Special Functions
Burst Cycles
Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read
or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to
simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the
internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in
a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
DA
DB
DE
DA
DC
/BB
DQA0-DQA8
DQB0-DQB8
CQ
/E
1
ADV
/BA
D
C
Address
A
B
ADV
CK
Write
Write
F
E
Write
Non-Write
Write
相關PDF資料
PDF描述
GS8170DW36AC-250I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-300 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-300I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-333 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-333I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
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GS8170DW36AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
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