參數(shù)資料
型號: GS8170DW36AC-250
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
中文描述: 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 6/32頁
文件大小: 766K
代理商: GS8170DW36AC-250
GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
6/32
2003, GSI Technology
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement
Pipeline mode NBT SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
W
Ba
Bb
Bc
Bd
Read
H
X
X
X
X
Write Byte A
L
L
H
H
H
Write Byte B
L
H
L
H
H
Write Byte C
L
H
H
L
H
Write Byte D
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort
L
H
H
H
H
SigmaRAM Double Late Write with Pipelined Read
ADV
DD
Read
Write
Read
Write
Read
C
D
F
E
CK
Address
A
B
/E
1
/W
DQ
QA
CQ
Key
QC
Hi-Z
Access
DB
相關(guān)PDF資料
PDF描述
GS8170DW36AC-250I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-300 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-300I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-333 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-333I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
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