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參數(shù)資料
| 型號： | GS8170DD36C-200I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 537K |
| 代理商： | GS8170DD36C-200I |
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GS8170DD36C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
8/29
2002, GSI Technology, Inc.
Burst Order
The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have
been accessed. SigmaRAMs always count in linear burst order.
Notes:
1.
2.
The burst counter wraps to initial state on the 3rd rising edge of clock.
The DDR SigmaRAM always begins an read or write at A0 = 0. A0 is internally set to 0 at the rising edge of clock and is not available to the
user.
Echo Clock
Σ
RAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data.
Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
Programmable Enables
Σ
RAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at V
DD
,
E2 functions as an active high enable. If EP2 is held to V
SS
, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
SRAMs can be made to look like one larger RAM to the system.
Linear Burst Order
A[1:0]
1st address (Rising Edge CK)
00
10
2nd address (Falling Edge CK)
01
11
3rd address (Rising Edge CK)
10
00
4th address (Falling Edge CK)
11
01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8170DD36C-250 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-250I | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-300 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-300I | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-333 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
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| GS8170DW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170DW36AC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
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