參數(shù)資料
型號(hào): GS4900B
廠商: Gennum Corporation
英文描述: SD Clock and Timing Generator with GENLOCK
中文描述: 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù): 60/95頁(yè)
文件大?。?/td> 898K
代理商: GS4900B
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
60 of 95
In the case of interlaced output formats, the programmed vertical start and stop
lines refer to the start and stop lines of the generated USER signal on the odd
fields. The start and stop lines of the USER signal on the even fields will be V_Start
- 1 and V_Stop - 1, respectively.
For example, if VID_STD[5:0] = 3, the odd fields will have 263 lines and the even
fields will have 262 lines. A user-defined vertical pulse programmed to start on line
12 and stop on line 17 will start on frame lines 12 and 274, and stop on frame lines
17 and 279.
The designated registers for programming each user signal are located in the host
interface beginning at address 57h. See
Section 3.10.3 on page 66
.
Figure 3-9: USER Programmable Output Signal
AND=0, OR=0, XOR=0 (default)
AND=0, OR=1
Shading indicates when USER_x signal is active
H
H
V_Start
V_Stop
AND=1
H
H
V_Start
V_Stop
H
H
V_Start
V_Stop
AND=0, OR=0, XOR=1
H
H
V_Start
V_Stop
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