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參數(shù)資料
| 型號： | GM5125 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 56/58頁 |
| 文件大小： | 1505K |
| 代理商： | GM5125 |
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***
Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
June 2002
47
C5115-DAT-01H
5
5
.
.
2
2
P
P
r
r
e
e
l
l
i
i
m
i
i
n
n
a
a
r
r
y
y
A
A
C
C
C
C
h
h
a
a
r
r
a
a
c
c
t
t
e
e
r
r
i
i
s
s
t
t
i
i
c
c
s
s
All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum
operating conditions used were:
T
DIE
= 0 to 125
°
C, Vdd = 2.35 to 2.65V, Process = best to worst, C
L
=
16pF for all outputs.
Table 22.
Maximum Speed of Operation
Clock Domain
Main Input Clock (TCLK)
DVI Differential Input Clock
ADC Clock (ACLK)
HCLK Host Interface Clock (2-wire protocol)
Input Format Measurement Clock (IFM_CLK)
Reference Clock (RCLK)
On-Chip Microcontroller Clock (OCM_CLK)
Display Clock (DCLK)
Max Speed of Operation
24 MHz (14.3MHz recommended)
165 MHz
162.5 MHz
5 MHz
50MHz (14.3MHz recommended)
200MHz (200MHz recommended)
100 MHz
135 MHz
Table 23.
Display Timing and DCLK Adjustments
DP_TIMING ->
Tap 0
(default)
Min
(ns)
Propagation delay from DCLK to DA*/DB*
Propagation delay from DCLK to DHS
Propagation delay from DCLK to DVS
Propagation delay from DCLK to DEN
Tap 1
Tap 2
Tap 3
Max
(ns)
4.5
4.5
4.5
4.5
Min
(ns)
0.5
0.5
0.0
0.5
Max
(ns)
3.5
3.5
3.5
3.5
Min
(ns)
-0.5
-0.5
-1.0
-0.5
Max
(ns)
2.5
2.5
2.5
2.5
Min
(ns)
-1.5
-1.5
-2.0
-1.5
Max
(ns)
1.5
1.5
1.5
1.5
1.0
1.0
0.5
1.0
Note: DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the propagation
delay between DCLK and its related signals.
Table 24.
2-Wire Host Interface Port Timing
Parameter
Symbol
MIN
TYP
MAX
Units
SCL HIGH time
SCL LOW time
SDA to SCL Setup
SDA from SCL Hold
Propagation delay from SCL to SDA
T
SHI
T
SLO
T
SDIS
T
SDIH
T
SDO3
1.25
1.25
30
20
10
us
us
ns
ns
ns
150
Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)
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