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參數(shù)資料
| 型號： | GM2120 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA/SXGA LCD Controller |
| 中文描述： | 的XGA / SXGA LCD控制器 |
| 文件頁數(shù)： | 26/51頁 |
| 文件大?。?/td> | 1379K |
| 代理商： | GM2120 |
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***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
19
C5110-DAT-01C
4.3.4 Sampling Phase Adjustment
The programmable ADC sampling phase is adjusted by delaying the HSYNC input to the
SDDS. The accuracy of the sampling phase is checked and the result read from a register.
This feature enables accurate auto-adjustment of the ADC sampling phase.
4.3.5 ADC Capture Window
Figure 12 below illustrates the capture window used for the ADC input. In the horizontal
direction the capture window is defined in IP_CLKs (equivalent to a pixel count). In the
vertical direction it is defined in lines.
All the parameters beginning with “Source” are programmed gm5110/20 registers values.
Note that the input vertical total is solely determined by the input and is not a programmable
parameter.
Reference
Point
I
S
S
V
Source Horizontal Total (pixels)
Source
Hstart
Source Width
Capture Window
Figure 12.
ADC Capture Window
The Reference Point marks the leading edge of the first internal HSYNC following the
leading edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are
derived from external HSYNC and VSYNC inputs.
Horizontal parameters are defined in terms of single pixel increments relative to the internal
horizontal sync. Vertical parameters are defined in terms of single line increments relative to
the internal vertical sync.
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