參數(shù)資料
型號(hào)： GM2110
廠商： Electronic Theatre Controls, Inc.
英文描述： XGA/SXGA LCD Controller
中文描述： 的XGA / SXGA LCD控制器
文件頁(yè)數(shù)： 44/51頁(yè)
文件大?。?/td> 1379K
代理商： GM2110
***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
37
C5110-DAT-01C
4.16.1 Host Interface Command Format
Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or
two nibbles respectively). These form an instruction byte, a device register address and/or
one or more data bytes. This is described in Table 19.
The first byte of each transfer indicates the type of operation to be performed by the
gm5110/20. The table below lists the instruction codes and the type of transfer operation. The
content of bytes that follow the instruction byte will vary depending on the instruction
chosen. By utilizing these modes effectively, registers can be quickly configured.
The two LSBs of the instruction code, denoted 'A9' and 'A8' in Table 19 below, are bits 9 and
8 of the internal register address respectively. Thus, they should be set to ‘00’ to select a
starting register address of less than 256, ‘01’ to select an address in the range 256 to 511,
and '10' to select an address in the range 512 to 767. These bits of the address increment in
Address Increment transfers. The unused bits in the instruction byte, denoted by 'x', should be
set to ‘1’.
Table 19. Instruction Byte Map
Operation Mode
Bit
7 6 5 4 3 2 1 0
0 0 0 1 x x A9 A8
0 0 1 0 x x A9 A8
Description
Write Address Increment
Write Address No Increment
(for table loading)
Allows the user to write a single or multiple bytes to a specified starting
address location. A Macro operation will cause the internal address pointer to
increment after each byte transmission. Termination of the transfer will cause
the address pointer to increment to the next address location.
Allows the user to read multiple bytes from a specified starting address
location. A Macro operation will cause the internal address pointer to
increment after each read byte. Termination of the transfer will cause the
address pointer to increment to the next address location.
1 0 0 1 x x A9 A8
1 0 1 0 x x A9 A8
Read Address Increment
Read Address No Increment
(for table reading)
0 0 1 1 x x A9 A8
0 1 0 0 x x A9 A8
1 0 0 0 x x A9 A8
1 0 1 1 x x A9 A8
1 1 0 0 x x A9 A8
0 0 0 0 x x A9 A8
0 1 0 1 x x A9 A8
0 1 1 0 x x A9 A8
0 1 1 1 x x A9 A8
1 1 0 1 x x A9 A8
1 1 1 0 x x A9 A8
1 1 1 1 x x A9 A8
Reserved
Spare
No operation will be performed
4.16.2 2-wire Serial Protocol
The 2-wire protocol consists of a serial clock HCLK (pin number 204) and bi-directional
serial data line HFSn (pin number 205). The bus master drives HCLK and either the master
or slave can drive the HFSn line (open drain) depending on whether a read or write operation
is being performed. The gm5110/20 operates as a slave on the interface.
The 2-wire protocol requires each device be addressable by a 7-bit identification number.
The gm5110/20 is initialized on power-up to 2-wire mode by asserting bootstrap pins
HOST_PROTOCOL=0 and the device identification number on HOST_ADDR(6:0) on the
rising edge of RESETn (see Table 18). This provides flexibility in system configuration with
multiple devices that can have the same address.
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