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參數(shù)資料
| 型號： | FS8107E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low Power Phase-Locked Loop IC |
| 中文描述： | 低功耗鎖相環(huán)集成電路 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 128K |
| 代理商： | FS8107E |
FS8107E
the wireless IC company
Page 9
June 2001
Quick-lock Signal (DB)
The quick-lock output signal, DB, is provided so that the PLL may achieve higher speed
locking. When connected, the DB output effectively doubles the charge pump current out-
put to the loop filter during the initial start-up of the PLL (when OPR first goes high).
Once the PLL phase error is within a specific tolerance, the quick-lock circuitry sets the
DB output to a high impedance state and the PLL continues toward lock with its normal
charge pump current.
Stand-by Mode
The stand-by mode for the PLL is entered by setting the OPR pin low and V
DD1
to 0 V
while the circuit is in operation. In the stand-by mode, the XIN and FIN amplifiers,
N
-
counter, and
R
-counter are stopped, the
N
- and
R
-counters are also reset, and the DO and
DB outputs are set to the high impedance state. As long as voltage is supplied to V
DD2
,
data loaded to the latches is kept. To exit from stand-by mode to normal operation, the
OPR pin must be set high and voltage must again be supplied to V
DD1
.
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| FS8108 | 制造商:PTC 制造商全稱:Princeton Technology Corp 功能描述:Low Power Phase-Locked Loop IC |
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| FS8170 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.5 GHz Low Power Phase-locked Loop IC |
| FS8308 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FRS. Pager. Multi-Channel system |
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