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參數(shù)資料
| 型號： | FS8107E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low Power Phase-Locked Loop IC |
| 中文描述： | 低功耗鎖相環(huán)集成電路 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 128K |
| 代理商： | FS8107E |
FS8107E
the wireless IC company
Page 6
June 2001
Functional Description
Programmable Input Frequency Divider
The VCO input to the FIN pin is divided by the programmable divider and then internally
output to the phase/frequency detector (PFD) as
f
V
. The programmable input frequency
divider consists of a ÷ 32/33 (
P
/
P
+1) dual-modulus prescaler and a 16-bit (
N
) counter,
which is further comprised of a 5-bit swallow (
A
) counter, and a 11-bit main (
B
) counter.
The total divide ratio,
M
, is related to values for
P
,
A
, and
B
through the relation
with
P
The minimum programmable divisor for continuous counting is given by
and the valid total divide ratio range for the input
32
31
×
992,
=
=
992 to 65535.
=
divider is
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable divider and then internally
output to the PFD as
f
R
. The programmable reference frequency divider consists of a fixed
÷ 8 (
S
) prescaler and a 13-bit reference (
R
) counter. The total divide ratio,
T
, is related to
values for
S
and
R
through the relation
The usable divisor range of reference counter is
total divide ratio range for the reference divider is
and therefore, the valid
(in steps of 8.)
40 to 65528
Serial Input Data Format
The divide ratios for the input and reference dividers are input using a 17-bit serial inter-
face consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The
format of the serial data is shown in Fig. 1. The data on the DATA line is written to the
shift register on the rising edge of the CLK signal and is input with MSB first, and the last
(17th) bit is used as the latch select control bit. The data on the DATA line should be
changed on the falling edge of CLK, and LE should be held low while data is being writ-
ten to the shift register. Data is transferred from the shift register to one of the frequency
divider latches when LE being set high. When the 17th bit is set low, data is loaded to the
16-bit
N
-counter latch, and when the 17th bit is set high, the 13 MSBs are loaded to the
M
P
1
+
(
)
A
P
B A
–
(
)
×
+
×
P
B
A,
+
×
=
=
B
P 1
–
(
A.
≥
)
×
M
T
S
R
×
8
R.
×
=
=
R
5 to 8191,
=
=
T
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