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參數(shù)資料
| 型號： | FS6051 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW-SKEW CLOCK FANOUT BUFFER ICs |
| 中文描述： | 低偏移時鐘扇出緩沖器集成電路 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 386K |
| 代理商： | FS6051 |
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April 1999
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SMBus
sequential registers, starting by default at Register 0. The
Block Write command, as noted in Figure 10, begins with
the seven-bit SMBus device address followed by a logic-
low R/W bit to begin a Write command. Following an ac-
knowledge of the SMBus address and R/W bit by the
slave device, a command code is written. It is defined
that all eight bits of the command code must be zero (0).
After the command code of zero and an acknowledge,
the host then issues a byte count that describes the
number of data bytes to be written. According to SMBus
convention, the byte count should be a value between 0
and 32; however this slave device ignores the byte count
value.
Following an acknowledge of the byte count, data bytes
may be written starting with Register 0 and incrementing
sequentially. An acknowledge by the device between
each byte of data must occur before the next data byte is
sent.
4.2.6
SMBus: Block Write
The Block Write command permits the
master to write several bytes of data to
4.2.7
The Block Read command, shown in Figure 11, permits
the master to read several bytes of data from sequential
SMBus: Block Read
registers, starting by default at Register 0. To perform a
Block Read procedure the R/W bit that is transmitted af-
ter the seven-bit SMBus address is a logic-low, as in the
Block Write procedure. The write bit resets the register
address pointer to zero. Following an acknowledge of the
SMBus address and R/W bit by the slave device, a com-
mand code is written. It is defined that all eight bits of the
command code must be zero (0).
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave SMBus ad-
dress is then resent, with the R/W bit set this time to a
logic-high, indicating to the slave that data will be read.
The slave will acknowledge the device address, and then
will expect a byte count value (which will be ignored).
Following the byte count value, the device will take com-
mand of the bus and will transmit all the data beginning
with Register 0. After the last byte of data, the master
does not acknowledge the transfer but does generate a
STOP condition.
If the master does not want to receive all the data, the
master can not acknowledge the last data byte and then
can issue a STOP condition of the next clock.
Figure 10: Block Write (SMBus)
A
A
A
DATA BYTE 1
WRITE Command
From bus host
to device
Acknowledge
Command Code
Acknowledge
Data
Acknowledge
Data
STOP Command
DATA BYTE N
Acknowledge
From device
to bus host
Byte Count
Acknowledge
START
Command
7-bit Receive
Device Address
W
S
DEVICE ADDRESS
A
A
BYTE COUNT = N
P
Figure 11: Block Read (SMBus)
A
W
A
R
A
A
START
Command
WRITE Command
From bus host
to device
Acknowledge
Command Code
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge
From device
to bus host
Byte Count
NO Acknowledge
Repeat START
READ Command
Acknowledge
7-bit Receive
Device Address
7-bit Receive
Device Address
S
DEVICE ADDRESS
A S
DEVICE ADDRESS
BYTE COUNT = N
A
DATA BYTE 1
DATA BYTE N
P
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相關代理商/技術參數(shù) |
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|---|---|
| FS6053 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW-SKEW CLOCK FANOUT BUFFER ICs |
| FS6054 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW-SKEW CLOCK FANOUT BUFFER ICs |
| FS605NA | 制造商:NETGEAR 功能描述:FS605NA FAST ENET SWITCH 制造商:NETGEAR 功能描述:NETGEAR FS605 - Switch - 5 x 10/100 - desktop |
| FS6070-01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Buffer/Driver |
| FS608NA | 制造商:TECH DATA 功能描述:NETGEAR FS608 - Switch - 8 x 10/100 - desktop |
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