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參數(shù)資料
| 型號： | FS6051 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW-SKEW CLOCK FANOUT BUFFER ICs |
| 中文描述： | 低偏移時鐘扇出緩沖器集成電路 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大小： | 386K |
| 代理商： | FS6051 |
XT
April 1999
4.5.99
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8.0 Application Information
8.1
The primary concern when designing the board layout for
this device is the reduction of electromagnetic interfer-
ence (EMI) generated by the 18 copies of the 100MHz
SDRAM clock. It is assumed the reader is familiar with
basic transmission line theory.
Reduction of EMI
8.1.1
To obtain the best performance, noise should be mini-
mized on the power and ground supplies to the IC. Ob-
serve good high-speed board design practices, such as:
Use multi-layer circuit boards with dedicated low im-
pedance power and ground planes for the device
(denoted as CLK VDD and CLK GND in Figure 18).
The device power and ground planes should be
completely isolated from the motherboard power and
ground planes by a void in the power planes.
Several low-pass filters using low impedance ferrite
EHDGV
DW0+]DUHUHFRPPHQGHGWRGHFR
ple the device power and ground planes from the
motherboard power and ground planes (MB VDD and
MB GND). The beads should span the gap between
the power and ground planes. Seven beads for
power and seven beads for ground are suggested
(14 total) so that the clock rise times (1V/ns) can be
maintained.
Place 1000pF bypass capacitors as close as possible
to the power pins of the IC. Use RF-quality low-
inductance multi-layer ceramic chip capacitors. Six
capacitors is optimal, one on each power/ground
grouping as shown in Figure 18.
Load similar clock outputs equally, and keep output
loading as light as possible to help reduce clock skew
and power dissipation.
Use equal-length clock traces that are as short as
possible. Rounded trace corners help reduce reflec-
tions and ringing in the clock signal.
The clock traces must never cross the void area be-
tween power/ground planes. Each trace must have a
complete plane (either VDD or GND) under the com-
plete length of the trace.
Layout Guidelines
u-
Figure 18: Board Layout
1
2
4
5
8
9
11
13
14
17
18
21
48
45
41
40
36
28
25
47
MB GND
MB VDD
31
32
44
35
38
24
CLK GND
CLK VDD
VOID
R
S
R
S
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
CLK GND
CLK VDD
MB GND
MB GND
MB VDD
MB VDD
Signal Layer
Component
Layer
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
8.1.2
A signal reflection will occur at any point on a PC-board
trace where impedance mismatches exist. Reflections
cause several undesirable effects in high-speed applica-
tions, such as an increase in clock jitter and a rise in
electromagnetic emissions from the board. Using a prop-
erly designed series termination on each high-speed line
can alleviate these problems by eliminating signal reflec-
tions.
Output Driver Termination
Figure 19: Series Termination
R
S
z
L
z
O
DRIVER
RECEIVE
LINE
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