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參數(shù)資料
| 型號(hào)： | FLG Series |
| 英文描述： | Flash Memory Card 256Kilobyte Through 5 Megabyte (Intel based)(256K字節(jié)-5M字節(jié)閃速存儲(chǔ)器卡（基于Intel）) |
| 中文描述： | 閃存卡256Kilobyte通過5兆字節(jié)（基于Intel）（256K字節(jié)，500萬字節(jié)閃速存儲(chǔ)器卡（基于英特爾）） |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 125K |
| 代理商： | FLG SERIES |
August 2000 Rev. 3 - ECO #13132
3
PCMCIA Flash Memory Card
FLG Series
PC Card Products
Pinout
Notes:
1. Wait#, BVD1 and BVD2 are driven high for compatibility
2. Shows density for which specified address bit is MSB. Higher order address bits are
no connects (i.e. 4MB A21 is MSB A22 - A25 are NC).
3. For the 3MB card the memory will wrap at the 4MB boundary, for the 5MB card the memory
will wrap at the 8MB boundary.
Mechanical
54.0mm
±
0.10
(2.126”)
10.0mm MIN
(0.400”)
1.6mm
±
0.05
(0.063”)
1.0mm
±
0.05
(0.039”)
1.0mm
±
0.05
(0.039”)
3.3mm
T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
Interconnect area
10.0mm MIN
(0.400”)
3.0mm MIN
85.6mm
±
0.20
(3.370”)
Substrate area
Pin Signal name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RDY/BSY
#
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin Signal name
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
Active
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
RFU
RFU
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2
RST
Wait#
RFU
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
O
I/O
I/O
I/O
I/O
I
I
O
LOW
LOW
LOW
N.C.
LOW
I
I
I
I
I
256KB(2)
512KB(2)
1MB(2)
2MB(2)
4MB(2,3)
LOW
N.C.
Vcc
Vpp1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
8MB(2,3)
N.C.
N.C.
N.C.
N.C.
N.C.
LOW(1)
O
I
O
I
O
O
I/O
I/O
O
O
(1)
(1)
I/O
I/O
I/O
O
HIGH
LOW
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