參數(shù)資料
型號(hào)： FIN224CMLX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 6/9頁(yè)
文件大?。?/td> 0K
描述： IC SER/DES 24-BIT BIDIR 40-MLP
標(biāo)準(zhǔn)包裝： 3,000
功能： 串行器/解串器
輸入類型： LVCMOS
輸出類型： 串行
輸入數(shù)： 24
輸出數(shù)： 1
電源電壓： 1.65 V ~ 3.6 V
工作溫度： *
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-MLP（6x6）
包裝： 帶卷 (TR)
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224C Rev. 1.0.9
6
SerD
es
FIN
224C
—
24-
B
it
Low-
P
ower
Serializer/D
eserializer
Electrical Specifications
Values valid for over supply voltage and operating temperature ranges unless otherwise specified. Typical values are tested
at TA = 25°C and VDD = 2.775V.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DC Parallel I/O Characteristics
VIH
Input High Voltage
0.65 x VDDP
VDDP
V
VIL
Input Low Voltage
GND
0.35 x VDDP
V
VOH
Output High Voltage
IOH = -2.0mA
VDDP = 3.3±0.30V
0.75 x VDDP
V
VDDP = 2.5±0.20V
VDDP = 1.8±0.18V
VOL
Output Low Voltage
IOH = -2.0mA
VDDP = 3.3±0.30V
0.25 x VDDP
V
VDDP = 2.5±0.20V
VDDP = 1.8±0.18V
IIN
Input Current
-5
5
A
DC Serial Characteristics
IODH
Output High Source Current
-1.75
mA
IODL
Output Low Source Current
0.95
mA
IOZ
Disabled Output Leakage Current
CKSO, DSO = 0V to VDDS,
S2 = S1 = 0V
±1
±5
A
IIZ
Disabled Input Leakage Current
CKSO, DSO = 0V to VDDS,
S2 = S1 = 0V
±1
±5
RTRM
CKSI, DS Internal Receiver Termination Resistor
100
Ω
Z
Serial Transmission Line Impedance
70
100
130
Ω
Power Characteristics
IDDA/SSER VDDA, VDDS Serializer Static Current
All DP and Control Inputs at 0V or No
CKREF, DIRI = 1
4.5
mA
IDDA/SDES VDDA, VDDS Derializer Static Current
All DP and Control Inputs at 0V or No
CKREF, DIRI = 0
5
mA
IDDSER
Dynamic Serializer Current
IDDSER = IDDA + IDDS + IDDP
CKREF = STROBE, DIRI = 1
10MHz
11
mA
20MHz
15
mA
IDDDES
Dynamic Deserializer Current
IDDSER = IDDA + IDDS + IDDP
CKREF = STROBE, DIRI = 0
10MHz
7
mA
20MHz
10
mA
IDD_PD
VDD Power-Down Current
IDD_PD = IDDA + IDDS + IDDP
S1 = S2 = 0 All Inputs at GND or VDD
0.1
A
AC Serializer, DIRI = 1 Specifications
fMAX
Maximum CKREF Frequency
2
20
MHz
fREF
CKREF Frequency Relative to
STROBE
1.1 x fSTROBE
20
MHz
tCPWH
CKREF Clock HIGH Time
0.2
0.5
T
tCPWL
CKREF Clock LOW Time
0.2
0.5
T
tCLKT
LVCMOS Input Transition Time
90
ns
tSPWH
STROBE Pulse Width HIGH/LOW
(Tx4) / 26
(Tx22) / 26
ns
tSTC
DP[n] Setup to STROBE
t
STC
t
HTC
STROBE
DP[24:1]
t
STC
t
HTC
t
STC
t
HTC
STROBE
DP[24:1]
2.5
ns
tHTC
DP[n] Hold to STROBE
2.0
ns
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