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參數(shù)資料
| 型號： | FIN210ACMLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SER/DES 10BIT 32-MLP |
| 標準包裝： | 3,000 |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVCMOS |
| 輸出類型： | 串行 |
| 輸入數(shù)： | 10 |
| 輸出數(shù)： | 1 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-MLP（5x5） |
| 包裝： | 帶卷 (TR) |
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
16 of 52
NXP Semiconductors
SC16IS741
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.
Register descriptions
The programming combinations for register selection are shown in Table 9.
[1]
MCR[7] can only be modified when EFR[4] is set.
[2]
Accessible only when ERF[4] = 1 and MCR[2] = 1, that is, EFR[4] and MCR[2] are read/write enables.
[3]
Accessible only when LCR[7] is logic 1.
[4]
Accessible only when LCR is set to 1011 1111b (0xBF).
Table 9.
Register map - read/write properties
Register name Read mode
Write mode
RHR/THR
Receive Holding Register (RHR)
Transmit Holding Register (THR)
IER
Interrupt Enable Register (IER)
Interrupt Enable Register
IIR/FCR
Interrupt Identification Register (IIR)
FIFO Control Register (FCR)
LCR
Line Control Register (LCR)
Line Control Register
MCR
Modem Control Register (MCR)[1]
Modem Control Register[1]
LSR
Line Status Register (LSR)
n/a
MSR
Modem Status Register (MSR)
n/a
SPR
Scratchpad Register (SPR)
Scratchpad Register
TCR
Transmission Control Register (TCR)[2]
Transmission Control Register[2]
TLR
Trigger Level Register (TLR)[2]
Trigger Level Register[2]
TXLVL
Transmit FIFO Level Register
n/a
RXLVL
Receive FIFO Level Register
n/a
EFCR
Extra Features Register
DLL
divisor latch LSB (DLL)[3]
divisor latch LSB[3]
DLH
divisor latch MSB (DLH)[3]
divisor latch MSB[3]
EFR
Enhanced Feature Register (EFR)[4]
Enhanced Feature Register[4]
XON1
Xon1 word[4]
XON2
Xon2 word[4]
XOFF1
Xoff1 word[4]
Xoff1 word[4]
XOFF2
Xoff2 word[4]
Xoff2 word[4]
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