參數(shù)資料
型號(hào)： FIN12ACMLX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
中文描述： LINE TRANSCEIVER, PQCC32
封裝： 5 X 5 MM, LEAD FREE, MO-220WHHD-4, MLP-32
文件頁(yè)數(shù)： 6/21頁(yè)
文件大小： 1819K
代理商： FIN12ACMLX
Preliminary
www.fairchildsemi.com
6
F
Deserializer Operation Mode
The operation of the deserializer is only dependent upon
the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the
operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE
signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals
that are inputs to the deserializer.
When operating in this mode the internal serializer circuitry
is disabled including the parallel data input buffers. If there
is a CKREF signal provided then the CKSO serial clock will
continue to transmit bit clocks.
Deserializer Operation:
DIRI equals 0
(Serializer Source: CKREF equals STROBE)
When the DIRI signal is asserted LOW the device will be
configured as a deserializer. Data will be captured on the
serial port and deserializer through use of the bit clock sent
with the data. The word boundary is defined in the actual
clock and data signal. Parallel data will be generated at the
time the word boundary is detected. The falling edge of
CKP will occur coincident with the data transition. The ris-
ing edge of CKP will be generated approximately 7 bit
times later. When no embedded word boundary occurs
then no pulse on CKP will be generated and CKP will
remain HIGH.
Deserializer Operation:
PwrDwn equals 1
DIRI equals 0
(Serializer Source: CKREF does not equal STROBE)
The logical operation of the deserializer remains the same
regardless of if the CKREF is equal in frequency to the
STROBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer will
however be different because it will have non-valid data
bits sent between words. The duty cycle of CKP will vary
based on the ratio of the frequency of the CKREF signal to
the STROBE signal. The frequency of the CKP signal will
be equal to the STROBE frequency. The falling edge of
CKP will coincident with data transition. The LOW time of
the CKP signal will be equal to
(7 bit times) of the
CKREF period. The CKP HIGH time will be equal to
STROBE period
of the CKREF period. Figure is repre-
sentative of a waveform that could be seen when CKREF
is not equal to STROBE. If CKREF was significantly faster
than additional non-valid data bits would occur between
data words.
FIGURE 4. Deserializer Timing Diagram
(Serializer Source: CKREF equals STROBE)
FIGURE 5. Deserializer Timing Diagram
(Serializer Source: CKREF does not equal STROBE)
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參數(shù)描述
FIN12Y WAF 制造商:Fairchild Semiconductor Corporation 功能描述:
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FIN1531MTC 功能描述:LVDS 接口集成電路 5V Hi Speed Driver LVDS 4Bit Differ RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
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