參數(shù)資料
型號(hào): FIN1218MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: LVDS 21-Bit Serializers/De-Serializers
中文描述: TRIPLE LINE RECEIVER, PDSO48
封裝: 6.10 MM, MO-153, TSSOP-48
文件頁(yè)數(shù): 5/17頁(yè)
文件大?。?/td> 434K
代理商: FIN1218MTD
5
www.fairchildsemi.com
F
Truth Tables
Transmitter Truth Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don’t Care
Z
=
High Impedance
F
=
Floating
Note 1:
The outputs of the transmitter or receiver will remain in a High Impedance state until V
CC
reaches 2V.
Note 2:
TxCLKOut
±
will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z).
Receiver Truth Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
P
=
Last Valid State
X
=
Don’t Care
Z
=
High Impedance
F
=
Failsafe Condition
Note 3:
The outputs of the transmitter or receiver will remain in a High Impedance state until V
CC
reaches 2V.
Note 4:
Failsafe condition is defined as the input being terminated and un-driven (Z) or shorted or open.
Note 5:
If RxCLKIn
±
is removed prior to the RxIn
±
data being removed, RxOut will be the last valid state. If RxIn
±
data is removed prior to RxCLKIn
±
being
removed, RxOut will be HIGH.
Inputs
TxCLKIn
Active
L/H/Z
Active
F
X
Outputs
TxIn
Active
Active
F
F
X
PwrDn (Note 1)
H
H
H
H
L
TxOut
±
L/H
L/H
L
L
Z
TxCLKOut
±
L/H
X (Note 2)
L/H
X (Note 2)
Z
Inputs
Outputs
RxIn
±
Active
Active
F (Note 4)
F (Note 4)
X
RxCLKIn
±
Active
F (Note 4)
Active
F (Note 4)
X
PwrDn (Note 3)
H
H
H
H
L
RxOut
L/H
P
H
P (Note 5)
L
RxCLKOut
L/H
H
L/H
H
H
相關(guān)PDF資料
PDF描述
FIN12ACGFX Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
FIN12AC Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
FIN12ACMLX Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
FIN1531M 5V LVDS 4-Bit High Speed Differential Driver
FIN1531MTC 5V LVDS 4-Bit High Speed Differential Driver
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