參數資料
型號: FDZ7064N
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: 30V N-Channel Logic Level PowerTrench BGA MOSFET
中文描述: 13.5 A, 30 V, 0.007 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝: ULTRA THIN, BGA-30
文件頁數: 2/6頁
文件大?。?/td> 186K
代理商: FDZ7064N
FDZ7064N Rev D4 (W)
Electrical Characteristics
Symbol
T
A
= 25°C unless otherwise noted
Test Conditions
Parameter
Min Typ Max Units
Off Characteristics
BV
DSS
BV
DSS
T
J
I
DSS
I
GSSF
I
GSSR
Drain
–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
V
GS
= 0 V,
I
D
= 250
μ
A, Referenced to 25
°
C
V
DS
= 24 V,
V
GS
= 0 V
V
GS
= 12 V,
V
DS
= 0 V
V
GS
= –12 V, V
DS
= 0 V
I
D
= 250
μ
A
30
V
21
mV/
°
C
μ
A
nA
nA
1
100
–100
On Characteristics
V
GS(th)
V
GS(th)
T
J
R
DS(on)
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
GS
,
I
D
= 250
μ
A, Referenced to 25
°
C
V
GS
= 4.5 V,
I
D
= 13.5 A
V
GS
= 10 V,
I
= 14.5 A
V
GS
= 4.5 V, I
D
= 13.5A, T
J
=125
°
C
V
DS
= 10 V,
I
D
= 13.5 A
I
D
= 250
μ
A
0.8
1.2
–4.6
6.1
5.4
9.0
92
2.0
V
mV/
°
C
m
8.0
7.0
13
g
FS
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
Drain
–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain
–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
t
rr
Diode Reverse Recovery Time
Q
rr
Diode Reverse Recovery Charge
Forward Transconductance
S
3843
522
209
pF
pF
pF
V
DS
= 15 V,
f = 1.0 MHz
V
GS
= 0 V,
10
9
71
18
31
8
7.4
20
18
114
32
43
ns
ns
ns
ns
nC
nC
nC
V
DD
= 15 V,
V
GS
= 10 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 15 V,
V
GS
= 4.5 V
I
D
= 13.5 A,
1.8
1.2
A
V
nS
nC
V
SD
V
GS
= 0 V,
I
F
= 13.5 A,
d
iF
/d
t
= 100 A/μs
I
S
= 1.8 A
(Note 2)
0.7
30
35
Notes:
1.
R
is determined with the device mounted on a 1 in2 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to the
circuit board side of the solder ball, R
θ
JB
, is defined for reference. For R
θ
JC
, the thermal reference point for the case is defined as the top surface of the copper
chip carrier. R
θ
JC
and R
θ
JB
are guaranteed by design while R
θ
JA
is determined by the user's board design.
a)
56°C/W when
mounted on a 1in
2
pad
of 2 oz copper
b)
119°C/W when mounted
on a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width <
300
μ
s, Duty Cycle < 2.0%
F
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