參數(shù)資料
型號： FAN5019B
廠商： Fairchild Semiconductor Corporation
英文描述： 6-Bit VID Controller 2-4 Phase VR10.X Controller
中文描述： 6期西元控制器2-4位的VR10.X控制器
文件頁數(shù)： 22/30頁
文件大?。?/td> 508K
代理商： FAN5019B
FAN5019B
PRODUCT SPECIFICATION
22
REV. 1.0.0 Jul/15/05
mF
F
V
m
A
nH
C
MIN
X
45
.
220
5
×
3
×
3
60
650
)
(
=
Ω
×
≥
μ
(
3
)
mF
F
nH
mV
m
V
s
V
m
mV
2
nH
×
C
MAX
X
9
23
220
1
650
250
3
×
6
×
3
×
5
×
150
1
5
×
6
×
3
250
Ω
650
2
2
)
(
=
Ω
×
+
×
×
≤
μ
μ
where K=4.6
Using eight 820μF A1-Polys with a typical ESR of 8m
Ω
,
each yields CX = 6.56μF with an RX = 1.0m
Ω
. One last
check should be made to ensure that the ESL of the bulk
capacitors (LX) is low enough to limit the initial high-
frequency transient spike. This can be tested using:
In this example, L
X
is 375pH for the eight A1-Poly capaci-
tors, which satisfies this limitation. If the L
X
of the chosen
bulk capacitor bank is too large, the number of MLC capaci-
tors must be increased.
Note: For this multi-mode control technique, “all-
ceramic” designs can be used as long as the conditions of
Equations 11, 12 and 13 are satisfied.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are V
GS(TH)
, Q
G
, C
ISS
, C
RSS
and R
DS(ON)
.
The minimum gate drive voltage (the supply voltage to the
FAN5009) dictates whether standard threshold or logic-level
threshold MOSFETs must be used. With V
GATE
~10V,
logic-level threshold MOSFETs (V
GS(TH)
< 2.5V) are
recommended. The maximum output current I
O
determines
the R
DS(ON)
requirement for the low-side (synchronous)
MOSFETs. With the FAN5019B, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (n
SF
). With conduction losses being dominant,
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
R
) and average total output
current (I
O
):
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can find
the required R
DS(ON)
for the MOSFET. For D-PAK
MOSFETs up to an ambient temperature of 50oC, a safe limit
for P
SF
is 1W–1.5W at 125oC junction temperature. Thus,
for our example (65A maximum), we find R
DS(SF)
(per MOSFET) < 8.7m
Ω
. This R
DS(SF)
is also at a junction
temperature of about 125oC, so we need to make sure we
account for this when making this selection. For our exam-
ple, we selected two lower side MOSFETs at 8.6m
Ω
each at
room temperature, which gives 8.4m
Ω
at high temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10% is
recommended), to prevent accidental turn-on of the synchro-
nous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN5009). The
output impedance of the driver is about 2
Ω
and the typical
MOSFET input gate resistances are about 1
Ω
–2
Ω
, so a total
gate capacitance should be less than 6000pF. Since there are
two MOSFETs in parallel, we should limit the input capaci-
tance for each synchronous MOSFET to 3000pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switch-
ing losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and off, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where n
MF
is the total number of
main MOSFETs:
Here, R
G
is the total gate resistance (2
Ω
for the FAN5009
and about 1
Ω
for typical high speed switching MOSFETs,
making R
G
= 3
Ω
) and CISS is the input capacitance of the
main MOSFET. Adding more main MOSFETs (nMF) does
not significantly help the switching loss per MOSFET since
the additional gate capacitance slows down switching. The
best way to reduce switching loss is to use lower gate capac-
itance devices.
The conduction loss of the main MOSFET is given by the
following, where R
DS(MF)
is the ON-resistance of the
MOSFET:
2
O
R
C
L
Z
X
×
μ
≤
(14)
(
3
)
pH
m
F
L
X
372
220
2
=
Ω
×
≤
(
)
)
(
2
2
12
1
1
SF
DS
SF
R
SF
O
SF
R
n
I
n
n
I
D
P
×
×
×
+
×
=
(15)
ISS
MF
n
G
MF
O
CC
n
SW
MF
S
C
n
R
I
V
f
P
×
×
×
×
×
×
=
2
)
(
(16)
)
(
2
2
)
(
12
1
MF
DS
MF
R
MF
O
MF
C
R
n
I
n
n
I
D
P
×
×
×
+
×
=
(17)
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