參數(shù)資料
型號(hào): FAN4800
廠商: Fairchild Semiconductor Corporation
英文描述: Low Start-Up Current PFC/PWM Controller Combos
中文描述: 低啟動(dòng)電流式PFC / PWM控制器功放音箱
文件頁(yè)數(shù): 15/19頁(yè)
文件大小: 369K
代理商: FAN4800
FAN4800
15
Leading/Trailing Modulation
Conventional PWM techniques employ trailing edge
modulation in which the switch turns on right after the
trailing edge of the system clock. The error amplifier
output is then compared with the modulating ramp up.
The effective duty cycle of the trailing edge modulation
is determined during the on-time of the switch. Figure 4
shows a typical trailing edge control scheme.
In the case of leading edge modulation, the switch is
turned off exactly at the leading edge of the system
clock. When the modulating ramp reaches the level of
the error amplifier output voltage, the switch is turned
on. The effective duty-cycle of the leading edge modu-
lation is determined during off-time of the switch. Figure
5 shows a leading edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1(SW 1) turns
off and switch 2(SW2) turns on at the same instant to
minimize the momentary no-load period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
the leading edge modulation method.
+
EA
EA
C MP
U1
RE F
VE AO
U3
DC
VIN
I1
I1
L1
S W1
D
C LK
DFF
Q
OS C
RAMP
C LK
U4
S W2
I2
I3
I4
I4
I4
RL
RAMP
TIME
VEAO
TIME
C 1
U2
R
Q
Figure 4. Typical Trailing Edge Control Scheme
+
EA
C MP
U1
REF
VEAO
U3
DC
VIN
I1
L1
S W1
D
C LK
DFF
Q
OS C
RAMP
C LK
U4
S W2
I2
I3
I4
I4
RL
RAMP
TIME
VEAO
TIME
C 1
U2
R
Q
Figure 5. Typical Leading Edge Control Scheme
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