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參數(shù)資料
| 型號： | FAN4800 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Start-Up Current PFC/PWM Controller Combos |
| 中文描述： | 低啟動電流式PFC / PWM控制器功放音箱 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 369K |
| 代理商： | FAN4800 |
FAN4800
13
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at
:
solving for C
T
* R
T
yields 1.96 * 10
-4
. C
T
is 390pF, and
R
T
is 51.1kohm, selecting standard components val-
ues.
The dead time of the oscillator adds to the maximum
PWM duty cycle (it is an input to the Duty Cycle Lim-
iter). With zero oscillator dead time, the maximum
PWM duty cycle is typically 47%. Take care not to
make C
T
too large which could extend the maximum
duty cycle beyond 50%. This can be accomplished by
using a stable 390pF capacitor for C
T
.
PWM Section
Pulse Width Modulator
The operation of the PWM section of the FAN4800 is
straightforward, but there are several points that should
be noted. Foremost among these is the inherent syn-
chronization of PWM with the PFC section of the
device, from which it also derives its basic timing. The
PWM is capable of current mode or voltage mode oper-
ation. In current mode applications, the PWM ramp
(RAMP2) is usually derived directly from a current
sensing resistor or current transformer in the primary of
the output stage, and is thereby representative of the
current flowing in the converter’s output stage. DC
I
LIMIT
, which provides cycle-by-cycle current limiting, is
typically connected to RAMP2 in such applications. For
voltage
mode operation, and certain specialized appli-
cations, RAMP2 can be connected to a separate RC
timing network to generate a voltage ramp against
which V
DC
will be compared. Under these conditions,
the use of voltage feed-forward from the PFC buss can
assist in line regulation accuracy and response. As in
current mode operation, the DC I
LIMIT
input is used for
output stage over current protection.
No voltage error amplifier is included in the PWM stage
of the FAN4800, as this function is generally performed
on the output side of the PWM’s isolation boundary. To
facilitate the design of opto-coupler feedback circuitry,
an offset has been built into the PWM’s RAMP2 input
that allows V
DC
to command a zero percent duty cycle
for input voltages below typical 0.95V.
PWM Current Limit
The DC I
LIMIT
pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output flip-flop is
reset by the clock pulse at the start of the next PWM
power cycle. Besides, when the DC ILIMIT triggers the
cycle-by-cycle current, it also softly discharges the volt-
age of soft-start capacitor. It will limit PWM duty cycle
mode. Therefore, the power dissipation will be reduced
during the dead short condition.
V
IN
OK Comparator
The V
IN
OK Comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on V
FB
is less
than its nominal 2.25V. Once this voltage reaches
2.25V, which corresponds to the PFC output capacitor
being charged to its rated boost voltage, the soft start
begins.
PWM Control (RAMP2)
When the PWM section is used in current mode,
RAMP2 is generally used as the sampling point for a
voltage representing the current in the primary of the
PWM’s output transformer. The voltage is derived
either from a current sensing resistor or a current trans-
former. In voltage mode, RAMP2 is the input for a ramp
voltage generated by a second set of timing compo-
nents (R
RAMP2
, C
RAMP2
), that will have a minimum
value of zero volts and a peak value of approximately
5V. In voltage mode operation, feed-forward from the
PFC output buss is an excellent way to derive the tim-
ing ramp for the PWM stage.
fOSC
100kHz
tRAMP
-------------------
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| FAN4800_06 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Start-Up Current PFC/PWM Controller Combos |
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| FAN4800A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:PFC/PWM Controller Combination |
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