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參數(shù)資料
| 型號(hào)： | F49B002UA-70N |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 2 Mbit (256K x 8) 5V Only CMOS Flash Memory |
| 中文描述： | 2兆位（256K × 8）5V的只有閃存的CMOS |
| 文件頁(yè)數(shù)： | 6/33頁(yè) |
| 文件大?。?/td> | 335K |
| 代理商： | F49B002UA-70N |
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EFS T
F49B002UA
Auto-select Mode
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4 6/33
The auto-select mode provides manufacturer and
device identification and sector protection verification,
through outputs on DQ7–DQ0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its
corresponding programming algorithm. However, the
auto-select codes can also be accessed in-system
through the command register.
When using programming equipment, this mode
requires V
ID
(11.5 V to 12.5 V) on address pin A9.
While address pins A3, A2, A1, and A0 must be as
shown in Table 3.
To verify sector protection, all necessary pins have to
be set as required in Table 3, the programming
equipment may then read the corresponding identifier
code on DQ7-DQ0.
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in Table 4. This method
does not require V
ID
. See “ Software Command
Definitions” for details on using the auto-select mode.
7.2 Software Command Definitions
Writing specific address and data commands or
sequences into the command register initiates the
device operations. Table 4 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of
WE
or
CE
, whichever happens later. All data is latched on
the rising edge of
WE
or
CE
, whichever happens
first. Refer to the corresponding timing diagrams in
the AC Characteristics section.
Table 4. F49B002UA Software Command Definitions
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Bus
Cycles
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (4)
1
RA
RD
-
-
-
-
-
-
-
-
-
-
Program
4
5555H AAH 2AAAH 55H
5555H
A0H
PA
PD
Chip Erase
6
5555H AAH 2AAAH 55H
5555H
80H
5555H AAH 2AAAH 55H 5555H
10H
Sector Erase
6
5555H AAH 2AAAH 55H
5555H
80H
5555H AAH 2AAAH 55H
SA
30H
Boot block lock
6
5555H AAH 2AAAH 55H
5555H
80H
5555H AAH 2AAAH 55H 5555H
40H
Reset 1(5)
1
XXXH F0H
-
-
-
-
-
-
-
-
-
-
Reset 2(5)
3
5555H AAH 2AAAH 55H
5555H
F0H
-
-
-
-
-
-
Auto-select
See Table 5.
Notes:
1.
X = don’t care
RA = Address of memory location to be read.
RD = Data to be read at location RA.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector.
2. Except Read command and Auto-select command, all command bus cycles are write operations.
3. Address bits A17–A16 are don’t cares.
4. No command cycles required when reading array data.
5. The two Reset command sequences have exactly the same effect, two are provided to meet the
requirements of difference companies and a range of applications.
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相關(guān)代理商/技術(shù)參數(shù) |
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| F49L004BA | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8) 3V Only CMOS Flash Memory |
| F49L004BA-70N | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8) 3V Only CMOS Flash Memory |
| F49L004BA-70T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8) 3V Only CMOS Flash Memory |
| F49L004BA-90N | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8) 3V Only CMOS Flash Memory |
| F49L004BA-90T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8) 3V Only CMOS Flash Memory |
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