參數(shù)資料
型號: F28F008SA-120
廠商: INTEL CORP
元件分類: DRAM
英文描述: 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY
中文描述: 1M X 8 FLASH 12V PROM, 120 ns, PDSO40
封裝: 10 X 20 MM, REVERSE, TSOP-40
文件頁數(shù): 15/33頁
文件大小: 466K
代理商: F28F008SA-120
28F008SA
RY/BY
Y
and Byte Write/Block Erase
Polling
RY/BY
Y
is a full CMOS output that provides a hard-
ware method of detecting byte write and block erase
completion. It transitions low time t
WHRL
after a
write or erase command sequence is written to the
28F008SA, and returns to V
OH
when the WSM has
finished executing the internal algorithm.
RY/BY
Y
can be connected to the interrupt input of
the system CPU or controller. It is active at all times,
not tristated if the 28F008SA CE
Y
or OE
Y
inputs
are brought to V
IH
. RY/BY
Y
is also V
OH
when the
device is in Erase Suspend or deep powerdown
modes.
290429–6
Bus
Command
Comments
Operation
Write
Byte Write
Setup
Data
e
40H (10H)
Address
e
Byte to be written
Write
Byte Write
Data to be written
Address
e
Byte to be written
Standby/Read
Check RY/BY
Y
V
OH
e
Ready, V
OL
e
Busy
or
Read Status Register
Check SR.7
1
e
Ready, 0
e
Busy
Toggle OE
Y
or CE
Y
to
update Status Register
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte write operation to reset the
device to Ready Array Mode
FULL STATUS CHECK PROCEDURE
290429–7
Bus
Command
Comments
Operation
Optional
Read
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
Check SR.3
1
e
V
PP
Low Detect
Standby
Check SR.4
1
e
Byte Write Error
SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 7. Automated Byte Write Flowchart
15
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