參數(shù)資料
型號: EVAL-ADV739XFEZ
廠商: Analog Devices Inc
文件頁數(shù): 17/108頁
文件大小: 0K
描述: BOARD EVAL FOR ADV739XFEZ
標準包裝: 1
系列: Advantiv®
主要目的: 視頻,視頻處理
嵌入式:
已用 IC / 零件: ADV7403
主要屬性: NTSC/PAL 數(shù)字視頻解碼器
次要屬性: 前端板,用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板
已供物品:
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 16 of 108
Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y0
Y1
Y2
Y3
a
Cr2
Cb2
Cr0
Cb0
b
Y OUTPUT
HSYNC
VSYNC
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
06234-
012
PIXEL PORT
Cb0
Y0
Cr0
Y1
a
HSYNC
VSYNC
b
Y OUTPUT
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
06234-
013
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