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參數資料
| 型號： | EVAL-ADV7180-32EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 59/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7180 |
| 標準包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，SDTV 視頻解碼器 - NTSC，PAL，SECAM |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7180 |
| 主要屬性： | CVBS（復合），Y/C（S 視頻）和 YPrPb（元件）輸入 |
| 次要屬性： | 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出 |
| 已供物品： | 板 |
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Data Sheet
ADV7180
Rev. I | Page 47 of 116
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
The HS begin (HSB) and HS end (HSE) registers allow the user
to freely position the HS output (pin) within the video line. The
values in HSB[10:0] and HSE[10:0] are measured in pixel units
from the falling edge of HS. Using both values, the user can
program both the position and length of the HS output signal.
HSB[10:0], HS Begin, Address 0x34[6:4], Address 0x35[7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 37). HSB is set to
00000000010b, which is two LLC clock cycles from count [0].
The default value of HSB[10:0] is 0x02, indicating that the HS
pulse starts two pixels after the falling edge of HS.
HSE[10:0], HS End, Address 0x34[2:0], Address 0x36[7:0]
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 37). HSE is set to
00000000000b, which is 0 LLC clock cycles from count [0].
The default value of HSE[10:0] is 00, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.
For example,
To shift the HS toward active video by 20 LLCs, add
20 LLCs to both HSB and HSE, that is,
HSB[10:0] = [00000010110], HSE[10:0] = [00000010100].
To shift the HS away from active video by 20 LLCs, add
1696 LLCs to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
Therefore, 1696 is derived from the NTSC total number of
pixels, 1716.
To move 20 LLCs away from active video, subtract 20 from
1716 and add the result in binary to both HSB[10:0] and
HSE[10:0].
PHS, Polarity HS, Address 0x37[7]
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active low.
When PHS is 1, HS is active high.
Table 64. HS Timing Parameters (See Figure 37)
Standard
Characteristic
HS Begin Adjust
HSB[10:0] (Default)
HS End Adjust
HSE[10:0] (Default)
HS to Active Video
LLC Clock Cycles, C
in Figure 37 (Default)
Active Video Samples/
Line, D in Figure 37
Total LLC Clock
Cycles, E in Figure 37
NTSC
00000000010b
00000000000b
272
720Y + 720C = 1440
1716
PAL
00000000010b
00000000000b
284
720Y + 720C = 1440
1728
E
ACTIVE
VIDEO
LLC
PIXEL
BUS
HS
Cr
Y
FF
00
XY
80
10
80
10
80
10
FF
00
XY
Cb
Y
Cr
Y
Cb
Y
Cr
4 LLC
D
HSB[10:0]
HSE[10:0]
C
E
D
SAV
ACTIVE VIDEO
H BLANK
EAV
05700-
028
Figure 37. HS Timing
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| EVAL-ADV7180-48EBZ-8P-CAL | 制造商:Analog Devices 功能描述: |
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| EVAL-ADV7180LFEBZ | 功能描述:BOARD EVAL FOR ADV7180 LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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