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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 61/92頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓模塊： | Process Control |
| 標準包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 64 of 92
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
or interrupt within a reasonable amount of time if the ADuC832
enters an erroneous state, possibly due to a programming error
or electrical noise. The watchdog function can be disabled by
clearing the watchdog enable (WDE) bit in the watchdog
control (WDCON) SFR. When enabled, the watchdog circuit
generates a system reset or interrupt (WDS) if the user program
fails to set the watchdog (WDE) bit within a predetermined
amount of time (see the PRE[3:0] bits in WDCON). The
watchdog timer itself is a 16-bit counter that is clocked directly
from the 32.768 kHz external crystal. The watchdog timeout
interval can be adjusted via the PRE[3:0] bits in WDCON. Full
control and status of the watchdog timer function can be con-
trolled via the watchdog timer control SFR (WDCON). The
WDCON SFR can only be written by user software if the double
write sequence described in the WDWR description (see Table 32)
is initiated on every write access to the WDCON SFR.
WDCON (Watchdog Timer Control Register)
SFR Address:
C0H
Power-On Default Value:
10H
Bit Addressable:
Yes
Table 32. WDCON SFR Bit Designations
Bit
Name
Description
[7:4]
PRE[3:0]
Watchdog timer prescale bits.
The watchdog timeout period is given by the following equation:
tWD = (2PRE × (29/fXTAL)).
where 0 ≤ PRE ≤ 7 and fXTAL = 32.768 kHz).
PRE3
PRE2
PRE1
PRE0
Timeout Period (ms)
Action
0
15.6
Reset or Interrupt
0
1
31.2
Reset or Interrupt
0
1
0
62.5
Reset or Interrupt
0
1
125
Reset or Interrupt
0
1
0
250
Reset or Interrupt
0
1
0
1
500
Reset or Interrupt
0
1
0
1000
Reset or Interrupt
0
1
2000
Reset or Interrupt
1
0
0.0
Immediate Reset
PRE[3:0] > 1000 = reserved.
[3]
WDIR
Watchdog interrupt response enable bit.
If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset when the watchdog
timeout period has expired. This interrupt is not disabled by the CLR EA instruction and it is also a fixed, high priority
interrupt. If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is
used to set the timeout period in which an interrupt is generated.
[2]
WDS
Watchdog status bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
[1]
WDE
Watchdog enable bit.
Set by user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog timeout
period, the watchdog generates a reset or interrupt, depending on WDIR.
Cleared under the following conditions: user writes 0, watchdog reset (WDIR = 0), hardware reset, or PSM interrupt.
[0]
WDWR
Watchdog write enable bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very next
instruction must be a write instruction to the WDCON SFR. See the Example Write Instruction section.
Example Write Instruction
CLR
EA
;disable interrupts while writing
;to WDT
SETB
WDWR
;allow write to WDCON
MOV
WDCON,
#72H
;enable WDT for 2.0 sec timeout
SETB
EA
;enable interrupts again (if rqd)
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