參數(shù)資料
型號(hào): EVAL-ADUC832QSZ
廠商: Analog Devices Inc
文件頁數(shù): 32/92頁
文件大?。?/td> 0K
描述: KIT DEV FOR ADUC832 QUICK START
產(chǎn)品培訓(xùn)模塊: Process Control
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC832
所含物品: 評(píng)估板,線纜,電源,軟件和文檔
其它名稱: EVAL-ADUC832QS
EVAL-ADUC832QS-ND
ADuC832
Data Sheet
Rev. B | Page 38 of 92
ADCCON3 (ADC Control SFR 3)
SFR Address:
F5H
SFR Power-On Default Value:
00H
Bit Addressable:
No
The ADCCON3 register controls the operation of various
calibration modes as well as giving an indication of ADC busy
status.
Table 18. ADCCON3 SFR Bit Designations
Bit
Name
Description
[7]
Busy
The ADC busy status bit is a read-only status bit that is set during a valid ADC conversion or calibration cycle. Busy is
automatically cleared by the core at the end of conversion or calibration.
[6]
GNCLD
Gain calibration disable bit. Set to 0 to enable gain calibration. Set to 1 to disable gain calibration.
[5:4]
AVGS[1:0]
Number of averages selection bits. These bits select the number of ADC readings averaged during a calibration cycle.
AVGS1
AVGS0
Number of Averages
0
15
0
1
0
31
1
63
[3]
RSVD
Reserved. This bit should always be written as 0.
[2]
RSVD
This bit should always be written as 1 by the user when performing calibration.
[1]
Typical
Calibration type select bit. This bit selects between offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for offset calibration.
Set to 1 for gain calibration.
[0]
SCAL
Start calibration cycle bit. When set, this bit starts the selected calibration cycle. It is automatically cleared when the
calibration cycle is completed.
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