參數(shù)資料
型號： EVAL-ADF4158EB1Z
廠商： Analog Devices Inc
文件頁數(shù)： 3/36頁
文件大小： 0K
描述： BOARD EVALUATION FOR ADF4158
標準包裝： 1
主要目的： 計時，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4158
主要屬性： 單路分數(shù)-N PLL
已供物品： 板
Data Sheet
ADF4158
Rev. G | Page 11 of 36
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
BUFFER
TO R-COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
08
72
8-
02
7
Figure 16. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 17. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AVDD
2k
RFINB
RFINA
087
28
-01
5
Figure 17. RF Input Stage
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 23 to 4095 are allowed.
25-BIT FIXED MODULUS
The ADF4158 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
fRES = fPFD/225
(1)
where fPFD is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible. Due to the architecture
of the Σ-Δ modulator, there is a fixed + (fPFD/226) offset on the
VCO output. To remove this offset, see the Σ-Δ Modulator
Mode section.
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R-counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). The RF VCO
frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/225))
(2)
where:
RFOUT is the output frequency of external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of binary 12-bit counter (23 to 4095).
FRAC is the numerator of the fractional division (0 to 225 1).
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(3)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
T is the REFIN divide-by-2 bit (0 or 1).
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
0
87
28
-01
6
Figure 18. RF N-Divider
R-COUNTER
The 5-bit R-counter allows the input reference frequency (REFIN)
to be divided down to produce the reference clock to the PFD.
Division ratios from 1 to 32 are allowed.
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